Semiconductor Bypass Wiring Reduces Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor chips advance in functionality, they face a wiring resource shortage, leading to increased wiring resistance, which restricts the flexibility of layout arrangements and circuit characteristics, particularly in designs where standard cells and macros operate with different power supply potentials.
Innovation Solution
The implementation of bypass wiring connected to through vias on the second surface side of the semiconductor substrate allows for the reduction of wiring resistance by providing an alternative path for power supply, thereby maintaining layout flexibility and improving circuit characteristics without dividing the global wiring layer resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring resources are miniaturized to prevent wiring resource shortage, then functionality is improved, but wiring resistance increases
Solution Approach 1:
The patent introduces bypass wiring on the back surface of the semiconductor chip, utilizing the third dimension (depth/thickness) to create alternative power supply paths. This allows power to reach standard cells through multiple routes: front surface wiring, through-vias, and back surface bypass wiring, thereby reducing overall wiring resistance without requiring front surface wiring miniaturization.
2Adaptability or versatility
If wiring resources are allocated to multiple circuits for higher functionality, then circuit characteristics are improved, but wiring resource shortage occurs leading to increased wiring resistance
Solution Approach 1:
The power supply network is segmented into multiple independent paths: front surface global wiring layers, through-vias, and back surface bypass wiring. This segmentation allows different regions and circuits to utilize different power supply paths, reducing contention for wiring resources and maintaining low resistance even as functionality increases.
3Adaptability or versatility
If standard cells are positioned non-overlapping with bump electrodes for layout flexibility, then design flexibility is improved, but power supply stability deteriorates due to increased wiring resistance
Solution Approach 1:
Through-vias act as intermediaries connecting the front surface bump electrodes to the back surface bypass wiring. This allows standard cells positioned anywhere on the chip to access power supply through the intermediary back surface wiring network, decoupling layout flexibility from power supply stability.
Data Source
AI summary
A semiconductor device includes a bypass wiring connected with a first through via and a second through via, on a second surface side of a semiconductor substrate that is an opposite side of a wiring structure formed on a first surface side of the semiconductor substrate.