Semiconductor Cache Abort Mechanism for Bufferless Coherency
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Solution Overview
Problem
In multiprocessor systems, the presence of multiple layers of caches increases circuit size and power consumption due to the need for replacement buffers between higher and lower caches, which can lead to performance degradation and increased chip size.
Innovation Solution
A semiconductor device architecture that eliminates the need for a replacement buffer by using a write-back port dedicated to write-back requests, allowing write-back requests to be processed independently of read requests, and employing an abort determination unit to manage conflicts and maintain data coherency without a replacement buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement buffers are provided between higher and lower caches, then data coherency can be maintained, but circuit size and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the replacement buffer component from the cache system. By using an abort determination unit that checks cache tags directly, the system removes the need for replacement buffers while maintaining data coherency through selective aborting of read requests that would conflict with write-back operations.
Solution Approach 2:
The abort determination unit acts as an intermediary between read requests and the cache data array. It intercepts read requests, checks cache tags to determine if data is being written back, and aborts conflicting reads without needing replacement buffers to hold data temporarily.
2Reliability
If replacement buffers are provided between higher and lower caches, then data coherency can be maintained, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming replacement buffer component from the system. The abort determination unit consumes less power than replacement buffers because it only performs tag checking and request aborting rather than maintaining full data copies and managing buffer operations.
3Speed
If multiple layers of caches are implemented, then processing speed can be improved, but device complexity increases
Solution Approach 1:
The patent simplifies the multi-layer cache system by extracting and removing the complex replacement buffer management logic. The abort determination unit provides a simpler mechanism that maintains data coherency across cache layers without the complexity of buffer allocation, validation, and data transfer operations.
4Area of stationary object
If replacement buffers are eliminated, then chip size decreases, but maintaining data coherency becomes more difficult
Solution Approach 1:
The abort determination unit serves as a simple intermediary that maintains coherency by checking cache tags and aborting conflicting read requests. This approach reduces chip size by eliminating replacement buffers while keeping coherency management simple through direct tag checking rather than complex buffer management.
Data Source
AI summary
A semiconductor device includes a core which includes a first cache and a second cache; and a third cache configured to connect to the core, wherein the core is configured to: hold a read instruction that is issued from the first cache to the second cache, hold a write-back instruction that is issued from the first cache to the second cache, process the read instruction and the write-back instruction, determine whether a target address of the read instruction is held by the first cache by using a cache tag that indicates a state of the first cache, and when data of the target address is held by the first cache, abort the read instruction until it is determined that data of the target address is not held by the first cache.