Semiconductor Device Cap Layer for Low OFF-Capacitance

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Solution Overview

Problem

In semiconductor devices like JPHEMTs, there is a trade-off between reducing ON-resistance (Ron) and OFF-capacitance (Coff), making it difficult to enhance carrier concentration in the channel layer while maintaining low OFF-capacitance and preventing electric field concentration at the PN junction, which affects the device's withstand pressure during the OFF state.

Innovation Solution

Incorporating a cap layer between the first low resistance region and the source or drain electrodes, which expands the carrier depletion region during the OFF-operation, thereby reducing OFF-capacitance and contact resistance, while maintaining low ON-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the concentration of impurities in the carrier supply region is increased to reduce ON-resistance, then the carrier concentration of the two-dimensional electron gas layer increases and ON-resistance decreases, but the depletion layer expansion is suppressed and OFF-capacitance increases

Engineering Contradiction:

ImproveON-resistanceVSAvoidOFF-capacitance

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The barrier layer is segmented into multiple functional regions: a carrier supply region closer to the channel layer and a second low resistance region farther from the channel layer. This segmentation allows independent optimization of carrier supply (for low ON-resistance) and depletion layer formation (for low OFF-capacitance), resolving the trade-off between these two parameters.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the barrier layer are assigned different impurity concentrations and functions. The carrier supply region has higher impurity concentration to supply carriers to the channel layer, while the second low resistance region has lower impurity concentration to facilitate depletion layer expansion. This local differentiation enables simultaneous achievement of low ON-resistance and low OFF-capacitance.

Inventive Principle:

Principle #3Local quality

2Speed

If the carrier concentration of the two-dimensional electron gas layer is increased to reduce ON-resistance, then electric field concentration at the PN junction occurs and withstand pressure decreases

Engineering Contradiction:

ImproveON-resistanceVSAvoidwithstand pressure

Core Design Contradiction:

SpeedVSStrength

Solution Approach 1:

The barrier layer is divided into a carrier supply region and a second low resistance region with different impurity concentrations. This segmentation distributes the electric field more evenly, preventing concentration at the PN junction while maintaining high carrier concentration in the channel layer for low ON-resistance and high withstand pressure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The carrier supply region provides high carrier concentration near the channel layer for low ON-resistance, while the second low resistance region has lower impurity concentration to reduce electric field concentration and increase withstand pressure. This local quality differentiation resolves the contradiction between ON-resistance and withstand pressure.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for reduced OFF-capacitance and ON-resistance, enhancing the transistor's characteristics and enabling smaller, lower power consumption wireless communication devices.

Implementation Method 1

This allows a carrier depletion region formed in the channel layer during the OFF-operation to be expanded from a region below the gate electrode to a region below the first low resistance region

Methodology Applied

Scientific EffectCarrier depletion region expansion:

Implementation Method 2

a two-dimensional electron gas layer in which electrons serving as carriers are confined at high concentration is formed at an interface, in the channel layer, on side of the barrier layer

Methodology Applied

Scientific EffectTwo-dimensional electron gas formation:

Implementation Method 3

By applying a voltage to the gate electrode to control the concentration of the two-dimensional electron gas layer, a current is modulated that flows between the source electrode and the drain electrode

Methodology Applied

Scientific EffectElectrical conduction control:

Data Source

PatentUS10396081B2Semiconductor device, antenna switch circuit, and wireless communication apparatus

Publication Date: 2019.08.27 SONY GROUP CORP

AI summary

A semiconductor device includes a layered body, a gate electrode, a source electrode, a drain electrode, and a cap layer. The layered body includes a channel layer and a first low resistance region. The channel layer is made of a compound semiconductor. The first low resistance region is provided in a portion on surface side of the layered body. The gate electrode, the source electrode, and the drain electrode are each provided on top surface side of the layered body. The cap layer is provided between the first low resistance region and one or both of the source electrode and the drain electrode.