Semiconductor Cap Unit with Non-Parallel Surfaces

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Solution Overview

Problem

Conventional semiconductor packages face challenges in reducing harmonic generation due to parasitic components during high-frequency signal processing, especially in microwave bands, leading to signal distortion and quality degradation.

Innovation Solution

A semiconductor package design featuring a hollow structure with non-parallel inner side surfaces and a cap unit made of high-resistance materials like silicon, which reduces harmonic generation by minimizing standing waves and insertion loss, and includes through electrodes for improved signal propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If conventional mounting structures are used with parallel inner side surfaces, then manufacturing is simpler, but harmonic generation increases due to standing waves

Engineering Contradiction:
Improveharmonic generationVSAvoidpackage structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by designing the cap unit with non-parallel inner side surfaces. Specifically, at least one inner side surface of the cap unit is inclined relative to the vertical direction, creating an asymmetric structure that prevents standing wave formation. This asymmetric geometry disrupts the parallel reflection paths that cause harmonics, thereby reducing harmonic generation while maintaining manageable package complexity

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent employs curvature principles by introducing inclined and non-parallel surfaces instead of flat parallel surfaces. The cap unit's inner side surfaces are designed with specific inclinations and curvatures that prevent uniform wave reflection, thereby eliminating standing wave patterns and reducing harmonic generation in the packaged semiconductor device

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Speed

If high-frequency signals are processed, then signal processing capability improves, but insertion loss increases due to parasitic components

Engineering Contradiction:
Improvesignal processing frequencyVSAvoidinsertion loss
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent introduces a porous material in the hollow space between the semiconductor chip and the cap unit. This porous structure serves multiple functions: it absorbs electromagnetic waves to reduce standing waves and harmonic generation, and it minimizes parasitic capacitance effects. The porous material's structure allows it to effectively dampen high-frequency signals without significant energy loss, thereby reducing insertion loss while maintaining high-frequency signal processing capability

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The patent uses a porous material as an intermediary substance filling the hollow space between the chip and cap unit. This intermediary material acts as a buffer that absorbs excess electromagnetic energy, reduces parasitic effects, and minimizes signal loss. The porous material mediates between the high-frequency signals and the package structure, preventing harmful interactions while allowing useful signal transmission

Inventive Principle:
Principle #24Intermediary (Mediator)

3Volume of moving object

If package size is reduced for integration, then device integration improves, but harmonic restraint becomes more difficult

Engineering Contradiction:
Improvepackage sizeVSAvoidharmonic generation
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry in a compact form by designing the cap unit with inclined inner side surfaces that create non-parallel reflections. This asymmetric geometry is scaled to fit within reduced package dimensions while maintaining its effectiveness in preventing standing wave formation. The inclined surfaces ensure that even in a small package volume, harmonic generation is restrained through disrupted wave reflection patterns

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent incorporates porous material within the compact hollow space of the reduced-size package. This porous structure efficiently absorbs electromagnetic waves and reduces harmonic generation even in limited volume. The high surface-area-to-volume ratio of the porous material makes it particularly effective in small packages, allowing harmonic restraint without compromising the reduced package size or integration goals

Inventive Principle:
Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively restrains harmonic generation, ensuring stable signal waveforms and reduced insertion loss, even at high frequencies, while allowing for smaller package sizes and increased integration.

Implementation Method 1

A semiconductor package design featuring a hollow structure with non-parallel inner side surfaces and a cap unit made of high-resistance materials like silicon, which reduces harmonic generation by minimizing standing waves and insertion loss

Methodology Applied
Scientific EffectStanding wave reduction: Resonance

Implementation Method 2

a cap unit made of high-resistance materials like silicon, which reduces harmonic generation by minimizing standing waves and insertion loss

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS9299627B2Semiconductor package having a cap unit with concave portion and method of manufacturing the same
Publication Date: 2016.03.29 KK TOSHIBA
  • US9299627B2 patent drawing
  • US9299627B2 patent drawing
  • US9299627B2 patent drawing

AI summary

A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.