Semiconductor Cap With Seed Layer Via Holes

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Solution Overview

Problem

Existing methods for semiconductor device packaging fail to efficiently form a cavity and plate via holes with a seed layer in silicon wafers thicker than 200 μm, leading to defects and instability in the interface between the silicon material and the plating material.

Innovation Solution

A cap for semiconductor device packages is designed with a body having a cavity and two via holes, each with a seed layer on its inner circumference, where the first via hole is plated using damascene electroplating and the second via hole is plated using back contact electroplating, with seed layers formed by sputtering Cr/Au or Ti/Cu materials, and the method involves forming these features using ICP RIE and CMP processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a via hole is formed on a substrate with thickness below 200 μm and a seed layer is formed on the inner circumference, then a fine plating layer can be obtained, but a cavity cannot be formed as required in packaging

Engineering Contradiction:

Improveplating layer finenessVSAvoidcavity formation capability

Core Design Contradiction:

Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The substrate is divided into two separate processing sides: the first surface undergoes via hole formation and plating to achieve fine plating layers, while the second surface undergoes cavity formation. This segmentation allows each process to be optimized independently, resolving the contradiction between achieving fine plating and forming cavities.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If a via hole is formed on a substrate with thickness over 300 μm, then a cavity can be formed, but a fine plating layer cannot be obtained because the seed layer is not formed on the inner circumference of the via hole

Engineering Contradiction:

Improvecavity formation capabilityVSAvoidplating layer fineness

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The substrate processing is segmented into two independent operations performed on opposite surfaces. The first surface is used for via hole formation and plating with seed layers to ensure fine plating quality, while the second surface is used for cavity formation. This allows thick substrates to be processed while maintaining both cavity formation capability and fine plating quality.

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If back contact plating is used to fill a via hole without a seed layer on the inner circumference, then plating can be performed, but alien substances are trapped on the interface causing defects

Engineering Contradiction:

Improveplating process simplicityVSAvoidinterface reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

A seed layer is formed on the inner circumference of the via hole before the plating process. This preliminary action ensures that the plating material has a proper foundation to bond to, preventing alien substance trapping at the interface and ensuring reliable bonding between the silicon substrate and plating material.

Inventive Principle:

Principle #10Preliminary action

4Productivity

If existing methods are used to plate via holes in wafers thicker than 200 μm, then the process can be completed, but the interface reliability between silicon material and plating material is weakened

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidinterface reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The substrate is processed from two opposite surfaces independently. The first surface receives via hole formation and plating with seed layers to ensure reliable interfaces, while the second surface receives cavity formation. This segmented approach maintains high processing efficiency for thick wafers while ensuring interface reliability through proper seed layer formation.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reliable and efficient formation of seed layers within via holes, preventing alien substance traps and enhancing the interface reliability between the silicon wafer and plating material, suitable for packaging devices with thicker wafers.

Implementation Method 1

seed layers formed by sputtering Cr/Au or Ti/Cu materials

Methodology Applied

Scientific EffectSputtering: Sputtering

Implementation Method 2

forming these features using ICP RIE

Methodology Applied

Scientific EffectPlasma: Plasma

Implementation Method 3

first via hole is plated using damascene electroplating and the second via hole is plated using back contact electroplating

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS7510968B2Cap for semiconductor device package, and manufacturing method thereof

Publication Date: 2009.03.31 SAMSUNG ELECTRONICS CO LTD

AI summary

A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a second seed layer formed on an inner circumference of a second via hole formed at a predetermined depth from the opposite surface to the cavity formation surface of the body, and plating materials filled in the first via hole and the second via hole.