Semiconductor Device Output Capacitance Dynamics for EMI Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor devices face challenges in reducing ringing and electromagnetic interference (EMI) due to extreme switching edges caused by low output capacitance, which can lead to increased switching losses and energy consumption.

Innovation Solution

A semiconductor device with an output capacitance characteristic featuring a maximum capacitance located at a voltage greater than 5% of the breakdown voltage, greater than 1.2 times the minimum capacitance, and a switchable electrical structure with a floating doping region and feedback path to manage charge carrier flow, reducing overshoot and EMI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If low output capacitance is used, then switching losses are reduced, but ringing and EMI increase due to extreme switching edges

Engineering Contradiction:
Improveswitching lossesVSAvoidringing and EMI
Core Design Contradiction:
Loss of energyVSObject-generated harmful factors

Solution Approach 1:

The patent applies dynamics by making the output capacitance variable rather than fixed. A floating doping region is introduced that changes the effective capacitance during switching transitions. The capacitance dynamically adjusts based on the depletion zone position, providing low capacitance during steady state for low losses, and increasing capacitance during transitions to reduce ringing and EMI.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the electrical parameter of output capacitance from a constant value to a variable value. By controlling the depletion zone position through the floating doping region, the effective capacitance parameter is changed during operation. This allows optimization of both switching losses and ringing/EMI performance by having different capacitance values at different operating points.

Inventive Principle:
Principle #35Parameter changes

2Speed

If extreme switching edges are produced, then switching speed is improved, but ringing and electromagnetic interference increase

Engineering Contradiction:
Improveswitching speedVSAvoidringing and EMI
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent uses dynamics to adjust the capacitance based on the switching state. During rapid transitions, the floating doping region modifies the depletion zone position to increase effective capacitance, which dampens the extreme edges and reduces ringing while still allowing fast switching. During steady state, the capacitance is minimized to maintain high switching speed capability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The floating doping region acts as a feedback mechanism where the depletion zone position automatically adjusts the capacitance based on the instantaneous voltage conditions. This self-regulating feedback provides increased capacitance when switching edges become too extreme, thereby reducing ringing and EMI without requiring external control circuits.

Inventive Principle:
Principle #23Feedback

3Object-generated harmful factors

If output capacitance is increased to reduce ringing, then EMI is reduced, but switching losses increase

Engineering Contradiction:
Improveringing and EMIVSAvoidswitching losses
Core Design Contradiction:
Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent resolves this contradiction by making capacitance dynamic rather than static. The floating doping region ensures that high capacitance is only present transiently during switching events when needed for reducing ringing and EMI, while low capacitance is maintained during steady state to minimize switching losses. This temporal separation of capacitance values eliminates the need to continuously maintain high capacitance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action by having the capacitance vary cyclically with each switching cycle. During each switching event, the capacitance temporarily increases to suppress ringing and EMI, then returns to a low value for the majority of the cycle. This periodic modulation of capacitance allows reduction of harmful effects without the continuous energy penalty of high static capacitance.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces ringing and EMI by increasing output capacitance at desired voltage ranges, minimizing switching losses and energy consumption while maintaining normal switching cycle efficiency.

Implementation Method 1

The feedback path is configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure

Methodology Applied
Scientific EffectCharge carrier flow control:

Implementation Method 2

At least a part of free charge carriers existing within the first doping region are removed from the first doping region as soon as the depletion zone reaches the first doping region

Methodology Applied
Scientific EffectDepletion zone effect:

Data Source

PatentUS11515414B2Semiconductor devices and methods for forming a semiconductor device
Publication Date: 2022.11.29 INFINEON TECH AUSTRIA AG
  • US11515414B2 patent drawing
  • US11515414B2 patent drawing
  • US11515414B2 patent drawing

AI summary

A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.