Semiconductor Pattern Inspection Using Core and Gap Capacitance
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Solution Overview
Problem
Conventional inspection methods for semiconductor structures after double patterning are labor-intensive and cannot be automated, making it difficult to inspect large quantities efficiently.
Innovation Solution
A method of forming semiconductor structures with pairs of target patterns connected by conductive lines on both sides, allowing for electrical inspection to measure core and gap capacitance values, ensuring structural uniformity and enabling automated inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If manual visual inspection is used to inspect semiconductor structures after double patterning, then inspection can be performed, but the process is labor-intensive and cannot be automated
Solution Approach 1:
The patent replaces manual visual inspection with an electrical inspection system that measures capacitance values. Conductive lines are formed to electrically connect to target patterns, enabling automated measurement of core capacitance and gap capacitance values through electrical probes, thereby substituting mechanical/manual inspection with an automated electrical measurement system
Solution Approach 2:
The patent introduces conductive lines as intermediaries between the inspection system and the target patterns. These conductive lines serve as mediators that enable electrical connection to the patterns, allowing the inspection system to measure capacitance values without direct contact with the delicate target patterns themselves
2Productivity
If manual visual inspection is used, then inspection can be performed, but it cannot inspect large quantities efficiently
Solution Approach 1:
The patent replaces manual visual inspection with an automated electrical measurement system that can rapidly measure capacitance values of multiple target patterns. The system uses conductive lines to electrically connect to patterns and automatically measures core capacitance and gap capacitance values, enabling high-throughput inspection without manual labor
Solution Approach 2:
The patent performs preliminary action by forming conductive lines and establishing electrical connections to target patterns before the inspection process. This preliminary setup enables subsequent automated measurements to be performed rapidly on large quantities of structures without repeated manual intervention
3Extent of automation
If electrical inspection with conductive lines is implemented, then automated inspection and large quantity inspection become possible, but additional structures must be added to the semiconductor device
Solution Approach 1:
The patent makes the conductive lines multi-functional: they serve both as electrical connection elements for automated inspection and as part of the overall device structure. The conductive lines are integrated into the device architecture, allowing them to fulfill both inspection and structural functions, thereby reducing the net increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables automated inspection of large numbers of semiconductor structures, improving yield and throughput by ensuring structural uniformity and stability through electrical inspection.
Implementation Method 1
the structural homogeneity of the core pattern can be detected by the core capacitance value and/or gap capacitance value obtained from electrical inspection
Data Source
AI summary
A method of forming a semiconductor structure is provided. The method includes following steps. A core pattern is formed on a target layer. Spacers are formed on sidewalls of the core pattern. The core pattern is removed to form an opening between the spacers. A portion of the target layer is removed by using the spacers as a mask to form a plurality of pairs of target patterns. After forming the pairs of target patterns, the spacers are removed, wherein a core opening is formed between each of pair of target patterns, and a gap opening is formed between adjacent pairs of the target patterns. A core capacitance value of corresponding target patterns on both sides of the core opening or a gap capacitance value of corresponding target patterns on both sides of the gap opening is measured to detect a structural uniformity of the core pattern.