Semiconductor Capacitor Comb-Like Electrode Sub-20 nm
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Solution Overview
Problem
As DRAM cell structures are miniaturized to sub-20 nm scales, conventional photolithography and etching processes struggle to form capacitors with high capacitance without increasing the occupied area, leading to complexity and reduced reliability in capacitor design.
Innovation Solution
A semiconductor capacitor structure with a comb-like bottom electrode and a dielectric layer is developed, where the comb-like electrode features tooth portions parallel to the substrate and a supporting portion perpendicular to it, increasing surface area without area expansion, and a method involving multi-layer structures, patterning, and trench formation to create these electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional photolithography and etching processes are used to form capacitors at sub-20 nm scale, then the occupied area is reduced, but the capacitance decreases due to inability to form tall vertical structures
Solution Approach 1:
The invention transitions from conventional planar capacitor structures to a comb-like three-dimensional structure with multiple tooth portions extending in the lateral direction. This dimensional change allows the capacitor to achieve high capacitance through increased effective electrode surface area in the lateral dimension rather than relying solely on vertical height, thereby maintaining high capacitance at sub-20 nm scale while occupying minimal substrate area.
Solution Approach 2:
The bottom electrode is segmented into multiple tooth portions forming a comb-like structure. This segmentation increases the effective surface area of the electrode without proportionally increasing the occupied footprint, as the tooth portions are arranged in a compact lateral configuration. The segmented structure enables high capacitance to be achieved within the constrained sub-20 nm area.
2Area of stationary object
If the critical dimension is reduced to sub-20 nm scale, then the occupied area decreases, but the structure becomes too small to allow formation of capacitor with tall vertical cylinder shape
Solution Approach 1:
Instead of forming tall vertical cylindrical structures that are difficult to manufacture at sub-20 nm scale, the invention employs a comb-like structure that extends laterally. This lateral extension approach is more compatible with conventional photolithography and etching processes at sub-20 nm nodes, as it does not require forming extremely high aspect ratio vertical structures that are beyond current manufacturing capabilities.
Solution Approach 2:
The comb-like structure features tooth portions with specific local geometries optimized for manufacturability at sub-20 nm scale. The tooth portions have controlled dimensions and spacing that are achievable with current lithography tools, while still providing sufficient effective surface area for high capacitance. This local geometric optimization enables ease of manufacture while maintaining electrical performance.
3Reliability
If taller vertical electrode structures are formed to increase capacitance, then the capacitance increases, but the occupied area increases and manufacturing complexity increases
Solution Approach 1:
The invention achieves high capacitance by utilizing the lateral dimension through comb-like tooth portions rather than increasing vertical height. This approach decouples the relationship between capacitance and occupied area, allowing high capacitance to be achieved while maintaining a compact footprint. The effective surface area is increased through lateral segmentation rather than vertical expansion.
Solution Approach 2:
The electrode is segmented into multiple comb teeth that are arranged laterally in a compact configuration. This segmentation provides large effective surface area for charge storage while keeping the overall footprint small. The segmented comb structure achieves high capacitance without requiring tall vertical structures or large occupied area.
Data Source
AI summary
The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.