Stacked Semiconductor Capacitor Electrode Leakage
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Solution Overview
Problem
Conventional semiconductor device capacitors face challenges in maintaining high cell capacitance with reduced electrode sizes, as doped polysilicon electrodes interact with high-k dielectric layers, leading to increased leakage current and signal noise due to high temperature processing.
Innovation Solution
A capacitor design featuring a stacked upper electrode structure comprising a metal layer, a doped polysilicon germanium layer, and a low-resistance material, such as tungsten, to minimize interaction with high-k dielectric layers and reduce leakage current, while maintaining optimal capacitance and resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped polysilicon is used as the upper electrode to achieve appropriate resistance, then the resistance characteristic is improved, but the leakage current increases due to interaction with high-k dielectric layers and high temperature processing
Solution Approach 1:
The upper electrode is divided into multiple layers: a first polysilicon layer for resistance control and a second polysilicon layer for low leakage current. This segmentation allows each layer to optimize for its specific function without compromising the other.
Solution Approach 2:
A barrier layer is introduced between the high-k dielectric layer and the polysilicon electrode to prevent direct interaction. This intermediary layer reduces leakage current while allowing the polysilicon layer to maintain its resistance characteristics.
2Reliability
If high-k dielectric layer is used to increase cell capacitance in reduced area, then the capacitance is improved, but the leakage current increases due to interaction with doped polysilicon
Solution Approach 1:
A barrier layer is positioned between the high-k dielectric layer and the polysilicon electrode to prevent direct interaction. This intermediary prevents the harmful chemical interaction that causes leakage current while allowing the high-k dielectric to maintain high capacitance.
Solution Approach 2:
The capacitor structure uses a composite of high-k dielectric material and polysilicon electrode with a barrier layer interface. This composite structure combines the high capacitance of the high-k material with the appropriate electrical characteristics of polysilicon while minimizing leakage through the barrier layer.
3Reliability
If high temperature heat treatment is applied to activate dopant in polysilicon electrode, then the resistance characteristic is improved, but the leakage current increases
Solution Approach 1:
The electrode structure is segmented into multiple polysilicon layers, allowing the first layer to undergo high temperature heat treatment for dopant activation and resistance control, while the second layer remains less affected by thermal processes, maintaining lower leakage current characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed capacitor design achieves improved electrical characteristics with reduced leakage current and appropriate resistance, enabling smaller capacitor sizes and more stable semiconductor device operation.
Implementation Method 1
a dielectric layer (150) formed on the lower electrode (140a)
Data Source
AI summary
Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.