3D Semiconductor Capacitor Layout for Accurate ESR Modeling
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Solution Overview
Problem
Semiconductor devices experience noise issues due to power-supply voltage changes, affecting signal transmission characteristics, and existing high-volume capacitors for noise cancellation are inefficient in reflecting resistance changes caused by routing patterns in Equivalent Series Resistance (ESR).
Innovation Solution
A capacitor design for semiconductor devices with a lower electrode layer, multiple upper electrode layers, dielectric layers with storage nodes, and line layers that measure equivalent series resistance (ESR) by modeling the resistance changes based on the routing pattern, forming a three-dimensional (3D) structure with resistors and capacitors in a distributed model circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If high-volume capacitors are formed in peripheral circuit region for noise cancellation, then noise reduction capability is improved, but Equivalent Series Resistance (ESR) calculation accuracy deteriorates due to inability to reflect resistance changes caused by routing patterns
Solution Approach 1:
The capacitor structure is segmented into multiple upper electrode layers with separate line layers and contacts for each layer. This segmentation allows the routing pattern resistance to be distributed and calculated for each segment, enabling accurate ESR calculation that reflects the actual resistance changes caused by different routing patterns.
Solution Approach 2:
The invention transitions from a conventional single-layer capacitor to a multi-layer three-dimensional structure with upper electrode layers stacked in the vertical direction. This dimensional change allows multiple routing patterns to be implemented in different layers, enabling accurate modeling and calculation of ESR variations due to routing patterns while maintaining noise cancellation capability.
2Ease of manufacture
If conventional capacitor design is used, then manufacturing simplicity is maintained, but ESR values do not accurately reflect routing pattern resistance changes
Solution Approach 1:
The multi-layer capacitor structure serves multiple functions: it provides noise cancellation capability, enables accurate ESR calculation by reflecting routing pattern resistance, and maintains compatibility with existing manufacturing processes. Each upper electrode layer with its line layers and contacts can be independently configured for different routing patterns while using the same fabrication steps.
Data Source
AI summary
A capacitor of a semiconductor device and a distributed model circuit for the same are disclosed. The capacitor includes a lower electrode layer, a plurality of upper electrode layers disposed over the lower electrode layer, a plurality of dielectric layers disposed between the lower electrode layer and each of the plurality of upper electrode layers, each dielectric layer configured to include a plurality of storage nodes, a plurality of line layers disposed over at least one of the plurality of upper electrode layers, and configured to receive a voltage for measuring an equivalent series resistance (ESR), and a plurality of contacts that electrically couple the plurality of line layers to the at least one of the plurality of upper electrode layers, wherein a resistance resulting from position information of the plurality of line layers and the plurality of contacts in a routing pattern corresponds to the ESR.