Semiconductor Devices Using EUV Lithography for Capacitor Integration
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Solution Overview
Problem
In DRAM devices, the integration of smaller cell capacitors due to low resolution ArF lithography limits the size of decoupling capacitors, resulting in insufficient electric capacitance.
Innovation Solution
Employing an EUV lithography process to form openings of different sizes in the cell and peripheral circuit regions, allowing for the creation of high-integration cell capacitors and increased electric capacitance in decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a double patterning process is performed to form small cell capacitors, then cell capacitor size is reduced, but decoupling capacitor electric capacitance decreases
Solution Approach 1:
The patent applies different opening sizes for different functional regions: small openings in the cell region for high-density cell capacitors, and large openings in the peripheral circuit region for high-capacitance decoupling capacitors. This local differentiation resolves the contradiction by allowing each region to have optimized dimensions for its specific function.
Solution Approach 2:
The patent utilizes the vertical dimension by forming cup-shaped lower electrodes that extend downward into the substrate. This increases the surface area for capacitance formation without increasing the planar footprint, allowing decoupling capacitors to achieve high electric capacitance even with limited peripheral circuit region area.
2Ease of manufacture
If ArF lithography is used for opening formation, then manufacturing process is simple, but opening size is insufficiently small
Solution Approach 1:
The patent segments the opening formation process into two independent stages: first forming openings in the cell region with smaller dimensions, then forming openings in the peripheral circuit region with larger dimensions. This segmentation allows each region to be optimized independently, achieving both small cell capacitor openings and sufficiently large decoupling capacitor openings within ArF lithography capabilities.
Data Source
AI summary
A semiconductor device includes gate structures, bit line structures, contact plug structures, first capacitors, and second capacitors. The gate structures are formed in a substrate including a cell region and a peripheral circuit region, and each of the gate structures extends in a first direction. The bit line structures are formed on the cell region of the substrate, and each of the bit line structures extends in a second direction. The contact plug structures are disposed in the second direction between the bit line structures on the substrate. The first capacitors are formed on the contact plug structures, respectively. The conductive pad is formed on the peripheral circuit region of the substrate, and is electrically insulated from the substrate. The second capacitors are formed on the conductive pad, and are disposed in the first and second directions.