Semiconductor Capacitor Formed in FEOL MEOL Processes
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Solution Overview
Problem
In semiconductor integrated circuits, the capacitance of capacitors is influenced when their areas are decreased, and existing processes for forming capacitors in BEOL stages do not efficiently achieve high capacitance with smaller occupied areas.
Innovation Solution
Capacitors are formed in MEOL and/or FEOL processes, utilizing dielectric layers with higher dielectric constants and smaller spacing intervals, allowing for higher capacitance and smaller area occupancy, with electrodes formed simultaneously with transistors and conductive contacts using specific processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitor area is decreased, then area occupancy is reduced, but capacitance decreases
Solution Approach 1:
The patent changes the dielectric constant parameter by using high-k dielectric materials (such as hafnium oxide, barium strontium titanate, or lead zirconate titanate) with dielectric constants significantly higher than conventional silicon dioxide. This parameter change allows the capacitor to achieve the same or higher capacitance with a smaller physical area, directly resolving the technical contradiction between area reduction and capacitance maintenance.
Solution Approach 2:
The patent transitions from planar capacitor structures to vertically stacked three-dimensional capacitor structures. By stacking multiple capacitor layers vertically, the effective capacitor area is increased without increasing the footprint area on the semiconductor substrate. This dimensional change allows higher capacitance density while maintaining small occupied area, effectively resolving the contradiction between area occupancy and capacitance.
2Ease of manufacture
If BEOL processes are used for capacitor formation, then manufacturing is simplified, but capacitance per area is insufficient
Solution Approach 1:
The patent segments the capacitor formation process into distinct stages that can be integrated into existing manufacturing flows. The high-k dielectric material is deposited as a separate layer, followed by separate electrode formation and patterning steps. This segmentation allows each process step to be optimized independently while maintaining compatibility with existing BEOL manufacturing processes, achieving both ease of manufacture and high capacitance density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in capacitors with higher capacitance and smaller occupied areas compared to BEOL processes, while being cost-effective due to simultaneous formation with existing transistor and contact processes.
Implementation Method 1
a dielectric layer 170... The capacitor 140 may include a first electrode 150 and a second electrode 160... The dielectric layer 170 may have a dielectric constant ranged from about 3.0 to about 3.5
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.