Semiconductor Capacitor Fabrication via Mold Structure Patterning
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Solution Overview
Problem
Semiconductor devices require capacitors with increased capacitance in limited areas, which is challenging due to the limitations in electrode surface area and dielectric film thickness, necessitating innovative methods to enhance capacitance without compromising reliability.
Innovation Solution
A method for fabricating semiconductor devices involves forming a lower electrode with an increased surface area by creating a mold structure, patterning it to form electrode holes, depositing a conductive layer, and forming a dielectric and upper electrode, while using protection layers to prevent unwanted reactions and maintain electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the surface area of the lower electrode is increased by forming a three-dimensional structure, then the capacitance is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar two-dimensional electrode structure to a three-dimensional structure by forming lower electrode holes that extend vertically through the mold structure. This dimensional change increases the electrode surface area and capacitance by utilizing the vertical dimension, allowing the lower electrode to contact the semiconductor substrate at the bottom of the holes while extending upward, thereby achieving higher capacitance within the same planar footprint.
Solution Approach 2:
The patent employs a nested structure where the lower electrode is formed within lower electrode holes that are defined by the mold structure. The mold structure itself is composed of nested layers (first mold layer, second mold layer, first supporting layer, second supporting layer) that are sequentially formed and patterned. This nesting approach allows complex three-dimensional electrode structures to be built systematically through layered fabrication processes.
2Reliability
If the lower electrode height is increased to enlarge effective surface area, then the capacitance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by first forming the complete mold structure (including first mold layer, second mold layer, and supporting layers) before forming the lower electrode. The mold structure serves as a pre-formed template that defines the exact geometry and dimensions of the lower electrode holes. This preliminary structuring allows the lower electrode to be formed with precise dimensional control, as the electrode simply fills the pre-defined space rather than requiring complex in-situ dimensional control during electrode formation.
Solution Approach 2:
The mold structure acts as an intermediary element that mediates between the fabrication process and the final lower electrode structure. The mold structure is formed first using conventional lithography and deposition processes, then serves as a template that guides the formation of the lower electrode. This intermediary approach simplifies the manufacturing process by decoupling the complex three-dimensional geometry definition (done in mold formation) from the electrode material deposition, thereby reducing manufacturing precision requirements for the electrode formation step itself.
3Reliability
If a protection layer is formed to prevent metal silicide formation, then the reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The protection layer serves as an intermediary barrier between the lower electrode and the polysilicon pattern. It prevents direct contact and unwanted chemical reactions (specifically metal silicide formation) between the electrode material and polysilicon, while allowing the polysilicon pattern to continue serving its function as an etch mask for forming the lower electrode holes. This thin intermediary layer adds minimal process complexity while significantly improving device reliability by preventing degradation of the lower electrode's electric characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the surface area of the lower electrode, enhancing capacitance and reliability of semiconductor devices by preventing metal silicide formation and maintaining optimal electric characteristics.
Implementation Method 1
the forming a protection layer may include performing a deposition process
Implementation Method 2
the forming a protection layer may include treating a surface of the polysilicon pattern with plasma generated from an oxygen gas or a nitrogen gas
Data Source
AI summary
Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.