Semiconductor Module Capacitor Layout for Self-Turn-On Prevention
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Solution Overview
Problem
Semiconductor devices face challenges in varying gate-source parasitic capacitance to prevent self-turn-on during high-speed switching, which affects power efficiency and reliability, especially in applications like non-insulative synchronous rectification converter circuits.
Innovation Solution
The semiconductor device incorporates a capacitor configuration that allows the specified pad to be connected or disconnected from the gate pad, thereby adjusting the gate-source parasitic capacitance, including a source-side electrode and a specified electrode facing each other with an insulation layer in between, to increase or maintain capacitance as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate-source parasitic capacitance is increased to prevent self-turn-on, then the reliability is improved, but the power efficiency deteriorates due to increased charging/discharging losses
Solution Approach 1:
The patent applies dynamics by making the gate-source parasitic capacitance adjustable rather than fixed. A switching element (third switching element) is introduced to dynamically connect or disconnect the capacitor between the gate pad and source pad, allowing the capacitance value to be changed based on operational requirements. This enables the system to prevent self-turn-on when needed while minimizing energy losses during normal operation.
Solution Approach 2:
The patent implements parameter changes by varying the gate-source parasitic capacitance value according to different operational states. The capacitor's connection status (connected or disconnected) changes the total capacitance parameter, allowing optimization between reliability (preventing self-turn-on) and power efficiency (reducing charging/discharging losses) based on circuit conditions.
2Loss of energy
If the gate-source parasitic capacitance is varied to optimize power efficiency, then the power efficiency is improved, but the device complexity increases due to additional capacitor and switching element
Solution Approach 1:
The patent applies universality by designing the capacitor and switching element to serve multiple functions. The capacitor not only adjusts parasitic capacitance but also integrates with the existing circuit topology. The third switching element controls both the capacitor connection and contributes to the overall switching function of the power converter, reducing the need for separate dedicated components.
Solution Approach 2:
The patent merges the capacitor and switching element into the existing circuit architecture rather than adding them as completely separate components. The capacitor is positioned to share space with other circuit elements, and the third switching element is integrated into the switching network, combining multiple functions (capacitance adjustment, switching control, and power conversion) into a unified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor device to selectively increase or maintain gate-source parasitic capacitance, preventing self-turn-on and optimizing power efficiency in different applications without altering the device design.
Implementation Method 1
a capacitor configured to increase the gate-source parasitic capacitance of the transistor when the specified pad is electrically connected to the gate pad
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulation layer arranged on the semiconductor substrate, a source pad formed on a head surface of the insulation layer and electrically connected to the source electrode, a drain pad formed on the head surface of the insulation layer and electrically connected to the drain electrode, a gate pad formed on the head surface of the insulation layer and connected to the gate electrode, a specified pad formed on the head surface of the insulation layer, and a capacitor. The capacitor includes a source-side electrode, electrically connected to the source electrode, and a specified electrode, electrically connected to the specified pad and arranged facing the source-side electrode.