Semiconductor Capacitor Shadow Mask Lithography
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Solution Overview
Problem
Existing semiconductor capacitors with large area plates and small footprints require a large number of lithography steps, leading to increased costs and higher defect rates due to non-uniform thickness issues in capacitor materials.
Innovation Solution
A semiconductor capacitor design utilizing shadow masks and a multi-chamber semiconductor processing system with only two lithography steps, where dielectric and metal layers are deposited with shadow masks to achieve uniform thickness and increased capacitance through interleaved structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conformal deposition is used to form capacitor plates lining an anisotropically dry etched opening, then large area plates with small footprint are achieved, but the deposited materials have non-uniform thickness and are very thin at the bottom corners, resulting in higher defect rates
Solution Approach 1:
The capacitor structure is divided into multiple separate plates rather than attempting to form a continuous conformal layer. The first capacitor plate includes first and second plates, and the second capacitor plate includes third and fourth plates, allowing each plate to be formed independently with uniform thickness through shadow mask deposition rather than conformal deposition around complex geometries
Solution Approach 2:
Shadow masks are introduced as intermediary tools to control the deposition process. The shadow masks define specific deposition regions and ensure uniform material thickness by blocking deposition in unwanted areas, eliminating the thickness non-uniformity problem associated with conformal deposition in anisotropically etched openings
2Reliability
If a large number of lithography steps are used to form interleaved capacitor plates, then capacitance is increased, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The shadow masks serve multiple functions: they define the patterns for multiple capacitor plates, control deposition thickness, and eliminate the need for separate lithography steps for each plate. This multi-functionality allows formation of complex interleaved structures with only two lithography steps instead of many
Solution Approach 2:
The shadow masks are prepared in advance with pre-defined patterns that correspond to multiple capacitor plates. This preliminary preparation allows all plate patterns to be deposited simultaneously in a single deposition process, eliminating the need for multiple sequential lithography steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of capacitors with large area plates and small footprints using two lithography steps, reducing costs and defect rates by ensuring uniform thickness and high capacitance values, specifically in the micro-farad range.
Implementation Method 1
a multi-chamber semiconductor processing system with only two lithography steps, where dielectric and metal layers are deposited with shadow masks to achieve uniform thickness
Data Source
AI summary
A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer.