Semiconductor Capacitor Using Self-Aligned Silicide Block Layer
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Solution Overview
Problem
The challenge in the semiconductor industry is to develop memory devices with decreased size and increased integration while maintaining good quality, particularly for one-time programmable memory cells, as existing technologies face complexity and cost issues in manufacturing and data storage.
Innovation Solution
A semiconductor capacitor and one-time programmable memory cell utilizing a resistive protection oxide layer or self-aligned silicide block layer as a capacitor dielectric layer, with a conductive plug and doped region as electrodes, fabricated without additional manufacturing processes, compatible with common complementary metal oxide-semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional capacitor structure with separate dielectric layer and electrodes is used, then the manufacturing process becomes complex and costly, but the device quality and reliability are maintained
Solution Approach 1:
The patent merges the capacitor dielectric layer with existing protection oxide layers or silicide block layers that are already part of the CMOS manufacturing process. By combining the capacitor dielectric function with these existing layers, the patent eliminates the need for separate capacitor fabrication steps, thereby simplifying the manufacturing process while maintaining device reliability
Solution Approach 2:
The patent makes existing layers serve multiple functions: the protection oxide layer or silicide block layer simultaneously acts as both a protective/blocking layer during manufacturing and as the capacitor dielectric layer. This multi-functionality reduces the total number of layers and processes required, directly addressing the manufacturing complexity issue
2Reliability
If additional manufacturing processes are added to create a separate capacitor structure, then the capacitor performance is improved, but the integration density decreases
Solution Approach 1:
By merging the capacitor structure with existing device components (using the source/drain region as one electrode and forming the dielectric from existing layers), the patent achieves high integration density without compromising capacitor performance. The capacitor is formed within the existing device footprint rather than adding separate structures
3Productivity
If the capacitor size is decreased to increase integration, then the integration density is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication where the capacitor dielectric layer is formed from existing layers that are already precisely positioned relative to the source and drain regions. The self-aligned silicide block layer or protection oxide layer automatically provides the correct positioning and thickness, eliminating the need for additional precision alignment steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and enhances integration by allowing the capacitor to be directly formed on the source/drain region, enabling reduced operating voltages and increased current density for efficient data storage.
Implementation Method 1
The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer
Data Source
AI summary
A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.