Semiconductor Capacitor With Stacked Electrodes And Etch Stops

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Solution Overview

Problem

Current semiconductor arrangements face challenges in efficiently forming capacitors within memory regions, particularly in achieving precise control over dielectric layers and electrode structures to optimize electrical connections and storage capabilities.

Innovation Solution

The semiconductor arrangement involves forming a capacitor structure with multiple dielectric layers, etch stop layers, and metal structures on a substrate, using techniques like atomic layer deposition and chemical vapor deposition to create a capacitor with specific dimensions and configurations that enhance electrical connections and storage capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple dielectric layers and etch stop layers are formed using atomic layer deposition and chemical vapor deposition, then manufacturing precision and reliability are improved, but device complexity and ease of manufacture worsen

Engineering Contradiction:
Improveprecise formation of capacitorsVSAvoidcapacitor structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The capacitor structure is divided into multiple functional layers including first and second dielectric layers, etch stop layers, and metal electrode layers. Each layer serves a specific function: dielectric layers for charge storage, etch stop layers for process control, and metal layers for electrical connections. This segmentation enables precise control over capacitor formation while maintaining manufacturability through specialized processing for each layer type.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar capacitor structures to three-dimensional vertically-stacked capacitor structures. Multiple dielectric and electrode layers are stacked vertically to increase storage capacity without increasing planar footprint. This dimensional change allows precise capacitor formation in the vertical dimension while maintaining compatibility with standard semiconductor manufacturing processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple dielectric layers and etch stop layers are formed using atomic layer deposition and chemical vapor deposition, then manufacturing precision is improved, but ease of manufacture worsens

Engineering Contradiction:
Improveprecise formation of capacitorsVSAvoidcapacitor fabrication ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Etch stop layers are formed preliminarily between dielectric layers during the deposition sequence. These etch stop layers are prepared in advance to facilitate subsequent etching processes and enable precise positioning of metal electrode layers. This preliminary action simplifies the overall manufacturing process by providing built-in process control features that guide subsequent fabrication steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Etch stop layers serve as intermediary layers between dielectric layers and metal electrode layers. These intermediary layers facilitate the etching process by providing selective etch targets, enabling precise formation of electrode structures without damaging adjacent dielectric layers. The intermediary etch stop layers simplify manufacturing by decoupling the deposition and etching processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If capacitor structures with multiple layers are formed, then storage capabilities are improved, but device complexity worsens

Engineering Contradiction:
Improvecharge storage capacityVSAvoidcapacitor structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple dielectric layers and metal electrode layers are nested vertically to form a stacked capacitor structure. Each dielectric layer is nested between metal electrode layers, creating a compact multi-layer configuration. This nesting approach increases charge storage capacity by multiplying the effective capacitor area without increasing the planar footprint, while the regular repeating pattern maintains manufacturing simplicity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The capacitor structure uses composite material stacks combining different dielectric materials with different electrical properties. High-k dielectric materials are combined with standard dielectric materials to enhance charge storage capacity. The composite material approach increases storage capability through material selection rather than increasing structural complexity.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the precise formation of capacitors with controlled dimensions and materials, improving electrical connections and storage capabilities within semiconductor memory regions, thereby enhancing the overall performance and efficiency of the semiconductor arrangement.

Implementation Method 1

using techniques like atomic layer deposition and chemical vapor deposition to create a capacitor with specific dimensions

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

using techniques like atomic layer deposition and chemical vapor deposition to create a capacitor with specific dimensions

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS9978754B2Semiconductor arrangement with capacitor
Publication Date: 2018.05.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9978754B2 patent drawing
  • US9978754B2 patent drawing
  • US9978754B2 patent drawing

AI summary

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.