Semiconductor Capacitor Structure With Straight-Wall Openings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of reducing leakage and improving process yield in highly integrated semiconductor structures, such as DRAM, is exacerbated by shrinking sizes and close distances, leading to manufacturing difficulties and compromised capacitor performance.
Innovation Solution
A method involving the use of oxide layers with varying dopant concentrations to control etching selectivity, forming non-tapered openings for conductive layers, and constructing a capacitor structure with a high aspect ratio without tapering, ensuring complete filling and improved capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between semiconductor structures is shortened to increase integration, then productivity and device density are improved, but leakage increases and manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by creating a dopant concentration gradient within the oxide layer, where the dopant concentration varies from the top surface to the bottom interface. This gradient provides different etching selectivity at different depths, enabling precise control of the opening profile while maintaining high integration density. The localized variation in dopant concentration allows the structure to simultaneously achieve tight pitch and low leakage.
Solution Approach 2:
The patent changes the physical-chemical parameters of the oxide layer by introducing a dopant with varying concentration through the layer thickness. This parameter change (dopant concentration gradient) directly controls the etching behavior during opening formation, enabling the creation of non-tapered openings with straight profiles that prevent leakage paths while maintaining small pitch dimensions.
2Ease of manufacture
If conventional etching is used to form openings, then manufacturing process is simple, but opening profile becomes tapered resulting in poor capacitance
Solution Approach 1:
The patent modifies the oxide layer's local properties by introducing a dopant concentration gradient, creating regions with different etching resistivity at different depths. This allows the etching process to proceed at different rates through the layer thickness, compensating for natural tapering effects and producing straight-walled openings without complex process steps.
Solution Approach 2:
The patent changes the etching parameter (etching selectivity) by varying the dopant concentration within the oxide layer. The dopant concentration is higher at the bottom interface and lower at the top surface, which reverses the natural etching rate gradient and produces non-tapered openings with improved capacitance while maintaining process simplicity.
3Ease of manufacture
If oxide layer with uniform dopant concentration is used, then manufacturing process is simple, but etching selectivity is insufficient to control opening profile
Solution Approach 1:
The patent introduces local quality variation in the oxide layer by creating a dopant concentration gradient rather than uniform doping. The dopant concentration is intentionally varied from the top surface to the bottom interface, providing depth-dependent etching selectivity that enables precise control of the opening profile while using standard doping techniques.
Solution Approach 2:
The patent changes the dopant concentration parameter within the oxide layer to create a gradient profile. This parameter change transforms the etching selectivity characteristic of the oxide layer, enabling the etching process to produce straight-walled openings. The doping method itself remains simple, but the resulting concentration distribution provides enhanced process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances capacitor performance by maintaining a straight profile, thereby improving capacitance and reducing leakage, thus addressing manufacturing challenges in high integration semiconductor devices.
Implementation Method 1
an etching selectivity of the lower portion of the oxide layer is greater than an etching selectivity of the upper portion of the oxide layer
Implementation Method 2
a concentration of the dopant gradually increases from an upper portion of the oxide layer to a lower portion of the oxide layer
Implementation Method 3
a concentration of an etchant of the wet etching process for etching the oxide layer is positively related to the concentration of the dopant in the oxide layer
Data Source
AI summary
Embodiments of this disclosure provide a semiconductor structure, including an active device layer disposed over a substrate and a capacitor structure disposed on the active device layer. The capacitor structure includes a first conductive layer disposed on the active device layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a third conductive layer disposed on the second conductive layer, a bottom inner insulating layer surrounding the first conductive layer in a top view, a second inner conductive layer surrounding the bottom inner insulating layer in the top view, and a third inner conductive layer surrounding the second inner conductive layer in the top view. Additionally, a method of manufacturing a semiconductor structure is also disclosed in this disclosure.