Semiconductor Capacitor Structures for 3D Memory Integration
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Solution Overview
Problem
There is a need for semiconductor devices with increased data storage capacitance and integration, particularly in vertically arranged memory cells and peripheral circuit regions.
Innovation Solution
The semiconductor device incorporates a capacitor structure with specific electrode configurations, including first and second strap portions and electrodes extending in vertical directions, and lower electrodes with high vertical height, integrated with circuit elements and interconnection structures to enhance electrostatic capacity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells and peripheral circuit regions are arranged vertically to increase integration, then device integration is improved, but electrical characteristics and electrostatic capacity may deteriorate
Solution Approach 1:
The capacitor structure extends in the vertical direction (third direction) with electrodes having high vertical height, transitioning from planar to three-dimensional configuration. This dimensional change increases electrostatic capacity without occupying additional planar area, thus maintaining high integration while improving electrical characteristics
Solution Approach 2:
The capacitor structure is integrated within the vertical stack of the memory device, with electrodes nested between the plate layer and bit line contact structure. This nesting approach allows the capacitor to occupy vertical space already utilized by other components, achieving both high integration and sufficient electrostatic capacity
2Reliability
If capacitor electrodes are designed with high vertical height to secure electrostatic capacity, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The vertical electrode structure serves multiple functions: it provides the capacitor electrodes for electrostatic storage, acts as part of the interconnection architecture, and integrates with the bit line contact structure. This multi-functionality reduces overall device complexity despite the three-dimensional configuration
Solution Approach 2:
The capacitor electrodes are merged with the bit line contact structure and interconnection layers, combining what could be separate components into an integrated structure. This merging simplifies the overall device architecture while maintaining the required electrostatic capacity through vertical extension
Data Source
AI summary
An example semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a substrate, an active region within the substrate, circuit elements on the substrate, an element isolation region defining the active region, impurity regions disposed within the active region on both sides of the circuit elements, an interconnection structure electrically connected with the circuit elements, and a capacitor structure spaced apart from the interconnection structure in a first direction. The second semiconductor structure includes a plate layer disposed on the first semiconductor structure, gate electrodes sequentially stacked and spaced apart from each other in a direction, perpendicular to an upper surface of the plate layer, on the plate layer, and channel structures extending through the gate electrodes in the perpendicular direction.