Semiconductor Structure With Capacitor Array for TSV Stress Attenuation

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Solution Overview

Problem

The integration of chips through Through-Silicon Vias (TSV) technology leads to deformation stress in semiconductor structures due to thermal expansion mismatch between conductive plugs and dielectric layers, affecting functional elements and causing structural damage.

Innovation Solution

A semiconductor structure incorporating a capacitor array surrounding the conductive plug to attenuate deformation stress, with multiple interfaces between upper and lower electrodes, reducing the impact on functional elements and ensuring structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If TSV technology is used to integrate chips in Z-axis direction, then interconnection between chips is improved, but deformation stress is generated affecting functional elements

Engineering Contradiction:
Improvechip integrationVSAvoiddeformation stress
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The capacitor array serves as an intermediary structure between the conductive plug and the functional elements. It absorbs and attenuates the deformation stress generated by thermal expansion mismatch, preventing direct transmission to sensitive functional elements while maintaining electrical interconnection functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention converts the harmful deformation stress into a beneficial effect by using the capacitor array to absorb and dissipate this stress. The multiple interfaces within the capacitor array structure transform the stress energy, converting what would be damaging mechanical stress into controlled deformation within the capacitor structure itself, thereby protecting functional elements.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If conductive plug is arranged in substrate and dielectric layer, then interconnection is achieved, but deformation stress affects functional elements

Engineering Contradiction:
ImproveinterconnectionVSAvoidfunctional element performance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The capacitor array is segmented into multiple capacitor units arranged in series, creating multiple interfaces between upper and lower electrodes. This segmentation allows the deformation stress to be distributed and attenuated across multiple boundaries, reducing the stress impact on any single functional element while maintaining overall interconnection reliability.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If capacitor array surrounds conductive plug, then deformation stress attenuation is improved, but device complexity increases

Engineering Contradiction:
Improvedeformation stress impactVSAvoidstructure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The capacitor array serves multiple functions simultaneously: it provides electrical capacitance for circuit operation, acts as a stress attenuation structure to protect functional elements, and serves as an isolation barrier between the conductive plug and surrounding structures. This multi-functionality reduces the need for separate dedicated stress relief structures, thereby limiting overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The capacitor array effectively attenuates deformation stress, minimizing its impact on functional elements and enhancing the performance and reliability of the semiconductor structure.

Implementation Method 1

When the deformation stress is transmitted in the capacitor array, the deformation stress needs to continuously pass through the interfaces or bypass the interfaces, so that relatively high transmission attenuation will be generated

Methodology Applied
Scientific EffectStress attenuation through interfaces:

Data Source

PatentEP4195262B1Semiconductor structure
Publication Date: 2024.11.20 CHANGXIN MEMORY TECH INC
  • EP4195262B1 patent drawingFigure 1~2
  • EP4195262B1 patent drawingFigure 3
  • EP4195262B1 patent drawingFigure 4

AI summary

Embodiments of the present application provide a semiconductor structure, comprising: a substrate and a dielectric layer located on the substrate; a conductive plug, a first portion of the conductive plug being located in the substrate and a second portion of the conductive plug being located in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug. The embodiments of the present application facilitate reducing effects of deformation stress generated by a conductive plug on a functional element.