Semiconductor Apparatus With Capacitor Voltage Equalization
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Solution Overview
Problem
The multistage configuration of FETs in high frequency switches enhances withstand voltage but enlarges the chip area, making it difficult to suppress manufacturing costs and results in uneven voltage distribution across FETs, limiting the effective enhancement of withstand voltage.
Innovation Solution
A semiconductor apparatus with a multistage configuration of FETs connected in series, where capacitors with decreasing capacitance are placed between each pair of FETs to equalize voltage distribution, preventing high voltage from being locally applied to any single FET, thereby allowing for increased withstand voltage without expanding the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a multistage configuration with multiple FETs connected in series is employed to enhance withstand voltage, then the withstand voltage is improved, but the chip area is enlarged
Solution Approach 1:
The patent changes the electrical parameters by introducing capacitors with specific capacitance values at different nodes of the FET stack. By carefully selecting the capacitance values (where C1 > C2 > C3...), the voltage distribution across the FETs is modified, enabling enhanced withstand voltage without requiring a proportional increase in the number of FETs, thus controlling chip area growth.
Solution Approach 2:
Capacitors are introduced as intermediary elements between the FETs in the series stack. These capacitors act as mediators that redistribute the voltage across the FET stack, preventing excessive voltage concentration on any single FET while maintaining the overall high withstand voltage capability, thereby achieving voltage enhancement without linearly increasing the device footprint.
2Strength
If a multistage configuration with multiple FETs connected in series is employed to enhance withstand voltage, then the withstand voltage is improved, but the manufacturing cost increases
Solution Approach 1:
By modifying the electrical parameters through the introduction of capacitors with optimized capacitance values, the patent achieves higher withstand voltage with a more efficient FET stack configuration. This reduces the total number of FETs required compared to a simple series connection, thereby lowering manufacturing costs while maintaining or enhancing voltage capability.
Solution Approach 2:
The patent applies different capacitance values at different positions in the FET stack (C1 > C2 > C3...), creating local variations in electrical characteristics. This localized optimization ensures that each section of the stack handles voltage appropriately, improving overall efficiency and reducing the total component count needed, which directly impacts manufacturing cost positively.
3Strength
If a multistage configuration with multiple FETs connected in series is employed, then the withstand voltage is enhanced, but the voltage distribution across FETs becomes uneven, limiting the effective enhancement of withstand voltage
Solution Approach 1:
The patent introduces capacitors with specifically designed capacitance values (C1 > C2 > C3...) to change the electrical characteristics of each node in the FET stack. This parameter modification compensates for the inherent voltage distribution imbalance in series-connected FETs, ensuring more uniform voltage sharing and enabling effective enhancement of withstand voltage without breakdown of individual devices.
Solution Approach 2:
By strategically placing capacitors with appropriate capacitance values at different nodes, the patent creates a voltage redistribution effect that approaches equipotential conditions across the FET stack. This reduces voltage concentration on any single FET, preventing breakdown and enabling the full potential of the multistage configuration to be realized for withstand voltage enhancement.
Data Source
AI summary
Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.