Self-Aligned Contact Etching Margin via Capping Layer
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices require sufficient margin in the etching process for forming self-aligned contacts while ensuring insulation between contacts and other semiconductor layers, which existing technologies struggle to achieve effectively.
Innovation Solution
A method for manufacturing semiconductor devices involves forming gate structures with conductive and capping layers, followed by the creation of insulation layers, block layers, and hardmask patterns, which allows for precise etching and self-alignment of contact holes, ensuring adequate margin and insulation through the use of materials like SiN, low-k materials, and high etch selectivity layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for forming self-aligned contacts, then the etching speed is maintained, but the margin for ensuring insulation between contact and other semiconductor layers is insufficient
Solution Approach 1:
The patent segments the etching process into multiple stages with different etching conditions. A first etching process forms initial contact holes with standard etching speed, followed by a second etching process that continues etching with modified conditions to achieve the required insulation margin. This segmentation allows optimization of both etching efficiency and final precision.
Solution Approach 2:
The patent performs preliminary actions by forming a capping layer over the conductive layer before the etching process. This capping layer serves as a protective structure that defines the etching boundary and ensures sufficient insulation margin is achieved during the etching process, preventing direct etching into the conductive layer.
2Reliability
If the etching margin is increased to ensure insulation, then the insulation reliability is improved, but the contact hole formation precision deteriorates
Solution Approach 1:
The patent introduces an intermediary structure - the capping layer - that mediates between the conductive layer and the etching process. This capping layer acts as a buffer that provides the necessary insulation margin while its precisely defined boundaries ensure that the etching process maintains accurate contact hole alignment with the gate structure.
Solution Approach 2:
The patent changes etching parameters between different etching stages. The first etching process uses parameters optimized for speed and initial hole formation, while the second etching process adjusts parameters to continue etching with controlled progression, maintaining alignment precision while achieving the required insulation depth.
3Manufacturing precision
If multiple etching stages are implemented to ensure insulation, then the manufacturing precision is improved, but the process complexity increases
Solution Approach 1:
The capping layer serves multiple functions simultaneously: it protects the conductive layer during etching, defines the etching boundary for precision, provides the insulation margin, and acts as a mask for the etching process. This multi-functionality reduces the need for additional separate structures or processes.
4Reliability
If the capping layer is used to protect the conductive layer, then the conductive layer protection is improved, but the etching selectivity requirement increases
Solution Approach 1:
The patent employs composite material structures with layers having different etching selectivities. The capping layer is made of material with high etching selectivity relative to the underlying layers, allowing it to be etched at a different rate and providing natural protection to the conductive layer. This selective etching property simplifies the overall process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method securely protects conductive layers during etching, ensures sufficient margin for self-aligned contact formation, and reduces the risk of short circuits, thereby enhancing the manufacturing process efficiency and reducing costs.
Implementation Method 1
The first insulation layer and the capping layer of the plurality of gate structures may have high etch selectivity with respect to each other, and the recessing top portions of the plurality of gate structures may include selectively etching the top portions of the plurality of gate structures with respect to the first insulation layer.
Implementation Method 2
The hardmask layer may have high etch selectivity with respect to the capping layer and the first insulation layer.
Implementation Method 3
The capping layer may include a low-k material or an ultra-low-k material. The low-k material may include SiBN, SiCN, SiBCN or SiOCN.
Implementation Method 4
forming a hardmask pattern on each of the plurality of the gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer
Data Source
AI summary
Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method includes forming a plurality of gate structures arranged in parallel on a substrate and being spaced apart from each other, each of the plurality of gate structures including a conductive layer and a capping layer formed on the conductive layer, forming a first insulation layer between each of the plurality of gate structures, recessing top portions of the plurality of gate structures, forming a block layer along a top surface of the first insulation layer and the recessed top portions of the plurality of gate structures, forming a hardmask layer on the block layer, forming a hardmask pattern on each of the plurality of gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer, and forming a second insulation layer along a top surface of the block layer and top surfaces of the hardmask patterns.