Semiconductor Capping Layer Segmentation for Low Contact Resistance
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Solution Overview
Problem
Existing MOS transistors face performance degradation due to high contact resistance between plugs and doped regions, caused by the large thickness of the initial capping layer and the resulting metal silicide layer, which reduces conductivity and degrades semiconductor device performance.
Innovation Solution
A method is developed to fabricate semiconductor devices by forming doped regions, a capping layer with conductive ions, and a dielectric layer, followed by etching to create a silicide region with reduced thickness, allowing for a self-aligned silicide process that forms a metal silicide layer in direct contact with the doped regions, thereby reducing resistance and improving conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the initial capping layer is formed with large thickness to ensure sufficient conductive ions, then the conductivity is improved, but the contact resistance between plugs and doped regions increases due to the resulting thick metal silicide layer
Solution Approach 1:
The capping layer is segmented into two distinct regions: a first capping layer region with larger thickness containing conductive ions, and a second capping layer region with smaller thickness at the via bottom. This segmentation allows the first region to provide sufficient conductive ions for conductivity while the second region minimizes contact resistance by forming a thinner metal silicide layer that enables better electrical contact between plugs and doped regions.
Solution Approach 2:
Different thicknesses of the capping layer are applied to different locations: the first capping layer region has a larger thickness to ensure sufficient conductive ions, while the second capping layer region has a smaller thickness to reduce contact resistance. This local quality variation optimizes both conductivity and contact resistance performance in their respective locations.
2Object-affected harmful factors
If the metal silicide layer thickness is reduced to improve contact resistance, then the contact resistance decreases, but the conductivity may be compromised due to insufficient conductive ions
Solution Approach 1:
The capping layer is divided into two functional regions: the first capping layer region provides sufficient conductive ions to maintain conductivity, while the second capping layer region with reduced thickness minimizes contact resistance. This segmentation resolves the contradiction by assigning different thicknesses to different functional requirements.
Solution Approach 2:
The capping layer exhibits local quality variation with different thicknesses in different regions. The first region has larger thickness for conductivity while the second region has smaller thickness for low contact resistance, allowing both requirements to be satisfied simultaneously in their respective locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach reduces contact resistance between plugs and doped regions, enhancing the electrical performance of semiconductor devices by ensuring a high concentration of conductive ions and a smaller thickness of the metal silicide layer, leading to improved current conduction.
Implementation Method 1
The initial capping layer contains conductive ions, and the conductive ions in the initial capping layer may be used to diffuse into the doped regions through an annealing process
Implementation Method 2
forming a metal silicide layer by performing a self-aligned silicide process on an entire silicide region. The metal silicide layer is in contact with the plurality of doped regions
Data Source
AI summary
A semiconductor device includes a base substrate; a plurality of doped regions formed in the base substrate; and a target capping layer formed on surfaces of the doped regions. The target capping layer includes a silicide region and a non-silicide region surrounding the silicide region, and the silicide region has a reduced thickness compared with a thickness of the non-silicide region. The semiconductor device further includes a metal silicide layer formed in the silicide region of the target capping layer and having the reduced thickness; a dielectric layer formed on the target capping layer and the base substrate; and a plurality of vias formed in the dielectric layer and connected to the metal silicide layer.