Semiconductor Package Capping Pattern Redistributing Chip Pads
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved reliability and durability, particularly in protecting chip pads from reactive materials and ensuring efficient electrical connections.
Innovation Solution
A semiconductor package is fabricated with a capping pattern that covers the chip pad, a passivation pattern exposing the chip pad, and a redistribution layer formed on the capping pattern, which includes insulation and redistribution patterns for electrical connectivity, preventing reactive material damage and enhancing package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board, then electrical connection is achieved, but reliability and durability are insufficient
Solution Approach 1:
The patent transitions from traditional wire/bump bonding (3D connection) to a planar redistribution layer approach (2D connection). The redistribution layer is formed on the same plane as the chip pad through photolithography and etching processes, eliminating the need for vertical wire bonds or solder bumps. This dimensional change simplifies the manufacturing process while improving electrical connection reliability.
Solution Approach 2:
The invention extracts and removes the bonding wires and bumps from the electrical connection structure. By eliminating these intermediate connection elements, the patent directly connects the chip pad to the printed circuit board through the redistributed copper traces, reducing potential failure points and improving overall reliability.
2Reliability
If chip pad is exposed to reactive materials, then electrical connection is maintained, but durability deteriorates due to reactive material damage
Solution Approach 1:
The patent introduces an intermediary protective layer (such as a barrier metal layer or protective coating) between the chip pad and reactive materials. This intermediary layer prevents direct contact between the reactive materials and the chip pad, thereby protecting the electrical connection from degradation while maintaining its functionality.
Solution Approach 2:
The invention applies preliminary protective measures by forming the protective layer on the chip pad before exposure to reactive materials. This pre-established protection prevents the harmful effects of reactive materials from affecting the chip pad, ensuring long-term durability of the electrical connection.
3Volume of moving object
If traditional packaging structure is used, then manufacturing is simple, but package size cannot be reduced
Solution Approach 1:
The patent merges the electrical connection function and the protective function into a single integrated structure. The redistribution layer serves both as the electrical connection path and as part of the protective system, eliminating the need for separate bonding wires, bumps, and protective coatings. This integration reduces overall package size while maintaining functionality.
Solution Approach 2:
The redistribution layer performs multiple functions simultaneously: it provides electrical connection, signal routing, and structural support. This multi-functionality allows the patent to reduce package size by eliminating redundant components that would otherwise be needed for each function separately.
Data Source
AI summary
A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.