Semiconductor Package Capture Land Prevents Molding Compound Penetration
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Solution Overview
Problem
Castellated semiconductor packages face issues with solder wetting due to molding compound penetration into plated-through holes, leading to defective joints and low yield rates during assembly, and require additional substrate bases, increasing costs.
Innovation Solution
A semiconductor package design featuring a capture land and interconnection structure that prevents molding compound entry into holes, allowing solder to wet properly and improving joint quality, while eliminating the need for additional substrate bases by integrating the substrate within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional castellated packages use plated-through holes for solder connection, then solder can wet the sidewalls and form fillets for joint inspection, but the molding compound penetrates the PTHs and prevents proper solder wetting
Solution Approach 1:
The package structure is segmented into distinct functional zones: the capture land area is separated from the PTH sidewalls by the encapsulant, creating a barrier that prevents molding compound penetration while preserving solder access to the capture land. This segmentation resolves the contradiction by spatially separating the solder connection function from the structural support function.
Solution Approach 2:
The encapsulant acts as an intermediary barrier between the molding compound and the PTH structures. It prevents the harmful penetration of molding compound into the PTHs while allowing the solder to reach the capture land for proper wetting and joint formation. This intermediary element resolves the contradiction by blocking the harmful path while preserving the useful function.
2Productivity
If castellated packages are sawn during singulation, then packages can be separated, but the Cu layer on the sidewall of the PTH may be ripped from the substrate base
Solution Approach 1:
The encapsulant is formed in advance to cover and protect the PTH sidewalls before the singulation process occurs. This preliminary protective action ensures that when the saw blade cuts through the substrate during singulation, the Cu layer on the PTH sidewalls is already shielded and cannot be ripped off, thus maintaining PTH integrity while enabling package separation.
Solution Approach 2:
The encapsulant provides beforehand cushioning and protection to the vulnerable Cu layer on the PTH sidewalls. By placing this protective layer prior to the mechanical stress of singulation, the design prevents damage to the PTH structures during the separation process, resolving the contradiction between productivity and manufacturing precision.
3Reliability
If additional substrate bases are used in castellated packages, then joint quality can be inspected, but manufacturing complexity and costs increase
Solution Approach 1:
The capture land is merged with the main substrate base, eliminating the need for separate additional substrate bases. The encapsulant is configured to expose the capture land while maintaining structural integrity, combining the functions of joint formation and inspection into a single integrated structure, thus reducing device complexity while preserving reliability.
Solution Approach 2:
The capture land serves multiple functions: it provides the solder connection surface, enables joint quality inspection through encapsulant exposure, and eliminates the need for additional substrate bases. This multi-functional design resolves the contradiction by making the existing structure universally serve both structural and inspection purposes, reducing overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances soldering reliability and yield rates by ensuring proper solder wetting and reduces manufacturing complexity and costs by integrating the substrate, thus addressing the defects and cost issues associated with traditional castellated packages.
Implementation Method 1
the encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip
Data Source
AI summary
A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.