Semiconductor Carrier Design Using Fine Redistribution Structure
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Solution Overview
Problem
Conventional semiconductor chip packaging methods result in thick, costly carriers due to the use of silicon substrates and through silicon vias, making it challenging to achieve miniaturization while maintaining manufacturing simplicity.
Innovation Solution
A carrier design featuring a fine redistribution structure with conductive connectors and an insulating layer, which omits the conventional silicon substrate, allowing for reduced thickness and cost, with optional core layers and through core vias to maintain conductivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon substrate and through silicon vias are used, then reliability and conductivity are maintained, but carrier thickness and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the silicon substrate and through silicon vias from the conventional carrier structure, replacing them with an insulating layer and conductive connectors formed directly on the fine redistribution structure. This extraction eliminates the thick silicon substrate while maintaining the essential conductivity and reliability functions through alternative structures.
Solution Approach 2:
The patent changes the material parameters and structural parameters of the carrier by transitioning from silicon-based materials to organic insulating materials (epoxy, polyimide, BCB) and forming conductive connectors with controlled dimensions (20-200 μm height). This parameter change enables thinner carrier construction while preserving electrical performance.
2Reliability
If silicon substrate and through silicon vias are used, then conductivity is maintained, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon substrates with cheaper organic insulating materials such as epoxy resin, polyimide, or BCB that can be formed using standard PCB fabrication processes. The conductive connectors are formed through cost-effective plating processes rather than expensive TSV fabrication, significantly reducing manufacturing costs while maintaining conductivity.
Solution Approach 2:
The patent changes the material composition from expensive silicon to cost-effective organic materials and adjusts the dimensional parameters of conductive elements to optimize both performance and manufacturing cost. The conductive connectors have controlled heights (20-200 μm) that balance conductivity requirements with manufacturing simplicity.
3Strength
If conventional packaging substrates are used, then structural support is provided, but miniaturization is difficult to achieve
Solution Approach 1:
The patent employs thin film structures for the insulating layer (formed from epoxy, polyimide, or BCB) and thin conductive connector structures that provide necessary structural support while minimizing thickness. This thin-film approach enables miniaturization while maintaining the mechanical strength and structural integrity needed for carrier functionality.
Solution Approach 2:
The patent creates a composite structure combining insulating materials (epoxy resin, polyimide, or BCB) with conductive materials (copper, aluminum, or alloy) in a layered configuration. This composite approach provides both structural support and electrical functionality in a miniaturized form factor, eliminating the need for thick conventional substrates.
4Ease of manufacture
If conventional carrier structures are used, then manufacturing process is established, but process complexity increases
Solution Approach 1:
The patent merges the formation of the insulating layer and conductive connectors into an integrated process sequence that can be performed using standard PCB fabrication steps (laminating, drilling, plating, etching). This merging of processes simplifies the overall manufacturing flow compared to separate silicon substrate processing and TSV formation, reducing process complexity while maintaining manufacturing capability.
Data Source
AI summary
A manufacturing method of a carrier for a semiconductor chip mounting thereon is provided. The method includes at least the following steps. A plurality of conductive connectors is formed on a fine redistribution structure to form a first portion, where the semiconductor chip is adapted to be mounted on the fine redistribution structure opposite to the conductive connectors. Each of the conductive connectors includes a bump and a solder cap formed on the bump, and the bump is directly connected to the fine redistribution structure. The first portion is disposed on a second portion, where the second portion includes a top redistribution structure directly connected to the solder cap and a second redistribution structure connected to the top redistribution structure, the first portion is disposed on the top redistribution structure, and a contact density of the top redistribution structure is denser than a contact density of the bottom redistribution structure.