Semiconductor Carrier with Insulating Adhesive Layer

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Solution Overview

Problem

Current semiconductor device assembly methods face challenges in effectively integrating and packaging power semiconductor chips, particularly in managing heat dissipation, mechanical stress, and electrical connectivity while maintaining the integrity of semiconductor chips with vertical structures.

Innovation Solution

The use of a carrier with an electrically insulating layer and an adhesive layer, combined with multiple deposition methods and intermediate conductive layers, allows for the secure attachment and electrical insulation of semiconductor chips, enabling efficient heat dissipation and mechanical stress reduction while allowing for electrical connectivity and control between chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor chips are directly mounted on a conductive carrier, then electrical connectivity is achieved, but heat dissipation and mechanical stress management deteriorate

Engineering Contradiction:
Improveelectrical connectivityVSAvoidheat dissipation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The device is segmented into distinct functional layers: a first semiconductor chip for power switching, a carrier for mechanical support and heat dissipation, and a second semiconductor chip for control functions. This segmentation allows each component to optimize its specific function without compromising the others.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The carrier acts as an intermediary between the power semiconductor chip and the control semiconductor chip. It provides mechanical support, heat dissipation pathways, and electrical isolation while enabling controlled electrical connectivity through conductive adhesive layers only where needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If semiconductor chips are directly mounted on a conductive carrier, then electrical connectivity is achieved, but mechanical stress management deteriorates

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmechanical stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The carrier exhibits local quality variations: it is electrically insulating in most areas to reduce mechanical stress and prevent unwanted electrical interference, but becomes locally conductive through adhesive layers only at specific mounting positions where electrical connectivity is required. This localized conductivity resolves the contradiction between connectivity and stress management.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The device employs composite material structures, including the carrier that combines mechanical support properties with controlled electrical conductivity through adhesive layers. The first semiconductor chip also integrates different materials (semiconductor layer, contact layers) to optimize both electrical and mechanical performance.

Inventive Principle:
Principle #40Composite materials

3Adaptability or versatility

If multiple semiconductor chips are integrated with different functions, then device functionality is improved, but device complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidintegration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The carrier serves multiple functions simultaneously: it provides mechanical support for the semiconductor chips, acts as a heat sink for thermal management, provides electrical isolation between chips, and enables controlled electrical connectivity through conductive adhesive layers. This multi-functionality reduces overall device complexity despite integrating multiple semiconductor chips with different functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration and packaging of power semiconductor chips by improving heat dissipation, reducing mechanical stress, and facilitating electrical connectivity, thereby increasing the reliability and performance of semiconductor devices.

Implementation Method 1

an adhesive layer (12) that is applied to the electrically insulating layer (11) as well as a first semiconductor chip (13) that is placed on the adhesive layer (12)

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Implementation Method 2

The carrier may be fabricated from metals or metal alloys, in particular copper, copper alloys, aluminum, aluminum alloys, or other materials. It may further be electrically conductive and may serve, inter alia, as a heat sink for dissipating the heat generated by the semiconductor chip.

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS7868465B2Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier
Publication Date: 2011.01.11 INFINEON TECHNOLOGIES AG
  • US7868465B2 patent drawing
  • US7868465B2 patent drawing
  • US7868465B2 patent drawing

AI summary

A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer applied onto the carrier, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip applied to the adhesive layer.