Semiconductor Device with Cascode Transistors on Insulating Substrate
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Solution Overview
Problem
Existing semiconductor devices face challenges such as wire resistance and inductance inhibiting high-speed operation and low ON-resistance, complex manufacturing processes, high costs, parasitic capacitance causing operational defects, and latch-up issues when combining compound semiconductor elements with silicon semiconductor elements.
Innovation Solution
A semiconductor device is fabricated using an insulating substrate with a compound semiconductor layer and a silicon layer, where transistors are formed in cascode connection without wires, simplifying the manufacturing process and reducing parasitic capacitance by using a sapphire substrate, and optimizing transistor layout for reduced resistance and effective space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chips are connected using wires, then electrical connection between compound semiconductor element and silicon semiconductor element is achieved, but wire resistance and inductance inhibit high-speed operation and low ON-resistance characteristics
Solution Approach 1:
The patent merges the compound semiconductor element and silicon semiconductor element onto a single insulating substrate, eliminating the need for external wire connections. This integration directly addresses the wire resistance and inductance issues by providing a low-resistance electrical connection path between the two semiconductor elements, thereby improving both operation speed and ON-resistance characteristics.
Solution Approach 2:
The insulating substrate serves as an intermediary platform that enables direct electrical connection between the compound semiconductor element and silicon semiconductor element without requiring external wires. This mediator approach resolves the contradiction by providing an integrated connection path that minimizes resistance and inductance while maintaining electrical functionality.
2Reliability
If vertically stacked laminate structure of silicon-silicon oxide film-SiC is used, then electrical connection is achieved, but epitaxial growth is in heavy use resulting in complex manufacturing process and higher manufacturing cost
Solution Approach 1:
The patent segments the semiconductor device into distinct functional layers on a common insulating substrate: a compound semiconductor layer for high-speed operation and a silicon layer for control functions. This segmentation allows each layer to be optimized independently while simplifying the manufacturing process compared to complex vertical epitaxial growth, reducing both process complexity and manufacturing cost.
Solution Approach 2:
Instead of using a vertical stacked laminate structure (three-dimensional arrangement), the patent transitions to a planar arrangement where compound semiconductor and silicon layers are formed on the same insulating substrate in different regions. This dimensional change from vertical stacking to lateral integration simplifies the manufacturing process by eliminating the need for complex epitaxial growth while maintaining electrical connection functionality.
3Ease of manufacture
If compound semiconductor element is formed directly on silicon single crystal substrate, then integration is achieved, but high voltages applied to compound semiconductor element affect silicon LSI through substrate causing operational defects and latch-up
Solution Approach 1:
The patent introduces an insulating substrate as an intermediary layer between the compound semiconductor element and the silicon layer. This insulating substrate acts as an electrical isolator that prevents high voltages applied to the compound semiconductor element from affecting the silicon LSI, thereby eliminating latch-up issues and operational defects while maintaining integration benefits.
Solution Approach 2:
The patent applies different material properties to different regions: the insulating substrate provides electrical isolation where needed, while the compound semiconductor and silicon layers provide their respective functional properties in their designated regions. This local differentiation of material qualities enables both integration and electrical isolation, resolving the contradiction between ease of manufacture and operational stability.
Data Source
AI summary
A semiconductor device includes insulating substrate; a compound semiconductor layer provided in a first region of a surface of the insulating substrate; and a silicon layer provided in a second region, differing from the first region, of the surface of the insulating substrate. The semiconductor device further includes: a first gate electrode provided on a surface of the compound semiconductor layer; a pair of conductive members provided at positions on the surface of the compound semiconductor layer to sandwich the first gate electrode between the pair of conductive members; a second gate electrode provided on a surface of the silicon layer; and a pair of diffusion layers provided at positions in the silicon layer to sandwich the second gate electrode between the pair of diffusion layers. One of the conductive members is electrically connected to one of the diffusion layers.