Semiconductor Chip Cavity Insulation for Leakage Current
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Solution Overview
Problem
Conventional semiconductor chip packaging methods face challenges in preventing leakage current due to the reduction in through silicon via diameter, requiring expensive lithography equipment and increasing product costs.
Innovation Solution
A semiconductor chip design featuring a conductive column part with a cavity formed around its end portion, where a first insulation layer is applied to expose the end portion for electrical connection to a back electrode, using organic or inorganic insulation materials to prevent leakage current without relying on advanced lithography equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the diameter of through silicon via is reduced to accommodate smaller semiconductor parts, then miniaturization is achieved, but leakage current increases due to insufficient insulation
Solution Approach 1:
The patent transitions from a planar insulation approach to a three-dimensional cavity structure. By forming a cavity around the conductive column and filling it with insulation material, the insulation is provided in the vertical dimension rather than relying solely on a thin horizontal layer, effectively preventing leakage current in miniaturized structures
Solution Approach 2:
The patent uses a composite structure combining conductive material (column part) with insulating material (filling the cavity). This composite approach allows the conductive column to maintain electrical connectivity while the surrounding insulating material prevents leakage current, solving the contradiction between miniaturization and leakage prevention
2Manufacturing precision
If expensive lithography equipment is used to achieve precise insulation layer opening, then leakage current is prevented, but product cost increases
Solution Approach 1:
The patent extracts the insulation layer opening step from the conventional process. Instead of forming a precise opening in the insulation layer through expensive lithography, the insulation material is directly formed to fill the cavity, eliminating the need for precise lithographic patterning while maintaining effective insulation
Solution Approach 2:
The patent replaces expensive lithography equipment with simpler, more cost-effective manufacturing methods. The cavity filling process can be achieved through less sophisticated equipment, reducing capital expenditure and manufacturing costs while achieving the same functional result
Data Source
AI summary
A semiconductor chip includes a substrate having a front surface and a back surface opposite the front surface, a conductive column part passing through the substrate from the front surface to the back surface, a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity, a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed, and a back electrode electrically connected to the exposed end portion of the conductive column part.