Cavity Formation in Semiconductor Devices for Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bulk silicon substrates suffer from poor device isolation and high junction capacitances, limiting their performance compared to silicon-on-insulator (SOI) substrates, which are more costly to produce.
Innovation Solution
A structure is formed with a first semiconductor layer, a device structure, a handle wafer, and a second semiconductor layer with a cavity between the handle wafer and the first semiconductor layer, surrounded by the second semiconductor layer, to achieve improved isolation. This involves epitaxial growth, shallow trench isolation, and selective etching to create a cavity that reduces junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bulk silicon substrates are used, then cost is reduced, but device isolation and junction capacitance performance deteriorate
Solution Approach 1:
The substrate is segmented into multiple functional layers: a bulk silicon handle wafer providing mechanical support and cost benefits, and a thin silicon layer on top containing the devices. This segmentation allows the device region to be electrically isolated while maintaining the cost advantages of bulk silicon processing.
Solution Approach 2:
A silicon dioxide layer is introduced as an intermediary between the device region and the bulk silicon handle wafer. This intermediate layer provides electrical isolation and improves device performance while allowing the structure to be fabricated using modified bulk silicon processes.
2Ease of manufacture
If bulk silicon substrates are used, then cost is reduced, but junction capacitance increases
Solution Approach 1:
The substrate structure is divided into a thick handle wafer and a thin device layer separated by an oxide layer. This segmentation creates electrical isolation that reduces junction capacitance while maintaining compatibility with bulk silicon manufacturing processes.
Solution Approach 2:
The silicon dioxide layer acts as an intermediary that electrically isolates the device region from the conductive bulk silicon handle, thereby reducing parasitic junction capacitances without requiring expensive SOI substrate processes.
3Reliability
If SOI substrates are used, then device isolation and junction capacitance performance are improved, but manufacturing cost increases
Solution Approach 1:
The invention creates a simplified version of SOI structure by forming a thin silicon layer on a bulk handle wafer with an oxide interface, replicating the beneficial electrical isolation properties of SOI substrates while using less complex and more cost-effective fabrication processes.
Solution Approach 2:
The invention changes the structural parameters by using a thick bulk silicon handle wafer instead of a thin SOI handle, and forms the isolation layer through oxidation rather than the complex processes required for true SOI substrates, thereby reducing cost while maintaining performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces junction capacitance and provides improved device isolation, mimicking the performance advantages of SOI substrates while maintaining the cost-effectiveness of bulk silicon substrates.
Implementation Method 1
a bonding layer configured to attach the handle wafer to the second semiconductor layer
Implementation Method 2
After thinning the first handle wafer, a cavity is formed in the second semiconductor layer that is arranged in the second semiconductor layer beneath the device structure
Implementation Method 3
forming a first semiconductor layer on a first side of a first handle wafer
Data Source
AI summary
Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.