Semiconductor Package With Cavity Substrate and Conductive Vias
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Solution Overview
Problem
Current semiconductor packaging techniques, such as fan-in WLCSP, fan-out WLCSP, PoP, CoWoS, and 3D IC, face limitations in integrating multiple functional dies due to constraints on pin number, complexity in building redistribution layers, and high costs associated with through silicon vias and tall pillars.
Innovation Solution
A 3D integrated fan-out panel-level package structure and fan-out wafer-level package structure are developed, utilizing a substrate with cavities and via holes formed by laser drilling, where dies are placed in cavities and connected via conductive vias with insulating and conductive structures, eliminating the need for tall pillars and through silicon vias, and enabling high aspect ratio via formation through electroplating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias and tall pillars are used for die integration, then electrical connection reliability is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent extracts the complex through silicon via and tall pillar structures from the integration process, replacing them with simpler wire bonding or flip chip techniques combined with substrate routing. This removes the problematic elements while maintaining the essential function of electrical interconnection between dies.
Solution Approach 2:
The substrate serves as an intermediary element that provides routing paths for electrical connections between multiple dies. Instead of direct vertical connections through silicon, the substrate acts as a mediator with controlled impedance traces that connect die pads, eliminating the need for complex TSV structures.
2Adaptability or versatility
If multiple functional dies are integrated using existing techniques, then system functionality is improved, but pin number constraints and redistribution layer complexity limit further integration
Solution Approach 1:
The patent transitions from planar redistribution layer routing to three-dimensional substrate routing with multiple routing layers and vias. This adds a vertical dimension to signal routing, allowing complex interconnections between multiple dies without increasing the footprint or requiring excessively complex single-layer RDL designs.
Solution Approach 2:
The substrate is designed to serve multiple functions simultaneously: mechanical support for dies, electrical routing between dies, thermal management pathway, and packaging structure. This multi-functionality reduces the need for separate dedicated structures for each function, simplifying overall system complexity.
3Area of moving object
If fan-in WLCSP technique is used, then chip size is reduced, but pin number is constrained by the chip perimeter
Solution Approach 1:
The patent uses three-dimensional substrate routing with multiple routing layers to increase the effective pin capacity. By routing signals through vertical vias and multiple copper layers in the substrate, the system achieves high pin counts without increasing the die or package footprint, effectively breaking the perimeter constraint.
Solution Approach 2:
The patent implements nested routing structures where multiple routing paths are contained within the substrate volume. Signal traces are nested across different layers, with via holes providing vertical interconnections between layers, effectively nesting the routing topology within a compact three-dimensional space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of multiple functional dies with a high product yield, overcoming the limitations of existing techniques by reducing manufacturing costs and simplifying the integration of dies with different functions, while providing a reliable and efficient electrical connection.
Implementation Method 1
enabling high aspect ratio via formation through electroplating
Implementation Method 2
utilizing a substrate with cavities and via holes formed by laser drilling
Data Source
AI summary
A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.