Semiconductor Package Cavity Venting for Defect-Resistant Underfill
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Solution Overview
Problem
The challenge is to create a compact, high-performance semiconductor package with improved structural stability and reduced defect occurrence, particularly for portable electronic devices, where multiple semiconductor chips need to be integrated in a small, lightweight package.
Innovation Solution
A semiconductor package design featuring a package substrate with cavities and vent holes, where under-fill layers fill spaces between chips and the substrate, and a molding layer surrounds the chips, providing structural stability and reducing defects through precise layer formation and thermocompression bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are mounted in a single package to meet high performance and high speed demands, then the functionality and performance of the package are improved, but the size and weight of the package increase
Solution Approach 1:
The patent implements a stacked package architecture where semiconductor chips are vertically stacked one on top of another, with underfill layers nested between them. This nested arrangement allows multiple chips to be integrated in a compact vertical configuration, significantly reducing the horizontal footprint and overall package weight while maintaining high performance through increased functional density
2Volume of moving object
If multiple semiconductor chips are mounted in a single package to achieve compact size, then the package dimensions are reduced, but the structural stability and reliability may deteriorate
Solution Approach 1:
The patent applies preliminary action by forming underfill layers between the semiconductor chips and the substrate before the final packaging process. These underfill layers are pre-positioned to provide mechanical support, stress relief, and structural stabilization to the stacked chip configuration, ensuring structural integrity is established early in the manufacturing process and maintained through subsequent steps
Solution Approach 2:
The patent employs composite material structures by combining semiconductor chips with underfill layers having different mechanical properties. The underfill layers act as composite materials that bridge the rigid chips and substrate, providing both mechanical support and flexibility to accommodate thermal expansion differences, thereby enhancing overall structural stability in the compact stacked configuration
3Strength
If underfill layers are used to fill spaces between chips and substrate to improve structural stability, then the mechanical strength is enhanced, but the manufacturing complexity and defect occurrence may increase
Solution Approach 1:
The patent segments the underfill structure into multiple distinct layers positioned between different chip stacks. Each underfill layer can be independently formed and optimized, allowing for simplified manufacturing of each individual layer while achieving cumulative structural benefits. This segmentation enables modular assembly and reduces the complexity of forming a single complex underfill structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a compact, high-performance semiconductor package with enhanced structural stability and reduced defect rates, allowing for efficient integration of multiple chips in a small form factor, meeting the demands for portable electronics.
Implementation Method 1
The first under-fill layer may extend along the first vent hole to fill the cavity
Implementation Method 2
A molding layer on the package substrate. The molding layer may surround the first semiconductor chip and the second semiconductor chip
Data Source
AI summary
Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.