Semiconductor Storage Device Cavity Wiring Parasitic Capacitance
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Solution Overview
Problem
The reduction in size of semiconductor storage devices leads to increased parasitic capacitance between wiring lines, causing signal delay, particularly in the peripheral circuit region, which existing methods fail to adequately address.
Innovation Solution
Formation of cavities in non-wiring regions between wiring patterns in the peripheral circuit region, defined by a second insulating film different from the interlayer insulating film, to reduce parasitic capacitance between wiring lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor storage device is reduced in size and microminiaturized to increase storage capacity, then the storage capacity is improved, but the parasitic capacitance between wiring lines increases causing signal delay
Solution Approach 1:
The patent extracts air (gas phase) from the non-wiring regions by forming cavities, replacing the solid interlayer insulating film with a gas-filled cavity. This extraction of material reduces the dielectric constant in the region between wiring lines, thereby reducing parasitic capacitance and signal delay while maintaining device miniaturization for increased storage capacity
Solution Approach 2:
The patent changes the physical parameter of the insulating medium in non-wiring regions from solid (interlayer insulating film with high dielectric constant) to gas (air cavity with low dielectric constant). This parameter change in the dielectric constant directly reduces parasitic capacitance between wiring lines, addressing the signal delay issue while maintaining the miniaturized structure for high storage capacity
Data Source
AI summary
A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.