1.5x Semiconductor Cell Structures for Propagation Delay Reduction
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Solution Overview
Problem
Current semiconductor design methodologies face challenges in optimizing the layout of standard cells to balance performance and layout constraints, particularly in achieving improved propagation delay while managing pin capacitance and maintaining design rules for parity in PMOS and NMOS rows.
Innovation Solution
The introduction of 1.5× cell structures that abandon parity in the number of PMOS and NMOS rows, incorporating two instances of one type of finFET technology and one instance of the other, along with non-uniform-width cell structures that discard uniform-width design rules, to enhance performance and reduce propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells are designed with uniform width and fixed height to facilitate automated placement, then ease of manufacture and automation are improved, but device complexity and performance optimization are limited
Solution Approach 1:
The cell structure is segmented into distinct functional regions: a first region containing PMOS transistors and a second region containing NMOS transistors. These regions can have different widths and are arranged in specific patterns (e.g., interdigitated or adjacent) to optimize performance while maintaining automated placement compatibility through standardized cell heights.
Solution Approach 2:
The patent introduces asymmetric cell structures where the first region and second region have different widths (e.g., 1.5x width ratio), breaking the traditional symmetric uniform-width design. This asymmetry enables better performance optimization for specific logic functions while the overall cell height remains standardized for automated placement.
2Manufacturing precision
If cell structures use uniform width design rules, then manufacturing consistency is improved, but propagation delay performance deteriorates
Solution Approach 1:
Different regions within the cell are assigned different width characteristics optimized for their specific function: the first region (PMOS) and second region (NMOS) have different widths tailored to their respective transistor requirements, while the overall cell maintains standardized height for manufacturing consistency.
Solution Approach 2:
The patent changes the width parameter locally within different regions of the cell structure. By allowing the first and second regions to have different widths (e.g., 1.5x ratio), the design optimizes carrier mobility and propagation delay for each transistor type while maintaining overall cell height consistency for manufacturing.
3Device complexity
If parity is maintained in PMOS and NMOS row counts, then design rule simplicity is improved, but performance optimization capability deteriorates
Solution Approach 1:
The patent extracts the parity constraint from the design rules, allowing odd numbers of transistor rows (e.g., 3 rows total: 2 in one region, 1 in the other). This removal of the parity requirement enables flexible performance optimization while maintaining standardized cell heights for automated placement.
4Productivity
If custom cells are designed with project-specific arrangements, then performance for specific functions is improved, but footprint size increases compared to standard cells
Solution Approach 1:
The patent creates a universal cell structure that can serve multiple functions by configuring the first and second regions with different transistor counts and arrangements. The same basic cell template can be adapted for various logic functions (AND, OR, NAND, NOR, etc.) by changing the transistor configuration within the standardized height framework, reducing the need for entirely custom cell designs.
Data Source
AI summary
A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.