Semiconductor Cell Array Design for Low On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Schottky barrier diodes (SBDs) face issues with increased on-resistance and suppressed high-speed operation due to narrow current paths and high contact resistance, particularly when attempting to reduce leakage current and on-voltage.
Innovation Solution
A semiconductor device design featuring a cell array with normal cells and contact cells, where the p-type buried layer is buried throughout the contact cell area, forming a ring-like shape around the normal cells, and the anode electrode is connected via a p+-type contact layer, reducing contact resistance and enhancing the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a p-type buried layer is provided inside an n-type semiconductor layer to reduce leakage current, then leakage current is reduced, but on-resistance increases due to narrow current path
Solution Approach 1:
The semiconductor layer is divided into multiple regions with different impurity concentrations, creating multiple current paths with different resistance characteristics. High-concentration regions provide low-resistance paths while low-concentration regions maintain the pn junction for leakage suppression.
Solution Approach 2:
Different regions of the semiconductor layer are assigned different impurity concentrations to perform different functions: low-concentration regions for leakage current suppression at the pn junction, and high-concentration regions for low on-resistance current conduction paths.
2Area of stationary object
If the width of the p-type buried layer is reduced, then the Schottky junction area is enlarged, but contact resistance between the connection conductor and buried layer increases
Solution Approach 1:
The contact layer is designed with locally high impurity concentration specifically at the contact region, allowing the buried layer to be narrow for large Schottky area while maintaining low contact resistance through the high-concentration contact layer.
Solution Approach 2:
Impurity concentration is increased in the contact layer to compensate for the reduced width of the buried layer, ensuring adequate electrical contact without requiring a wide buried layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces leakage current and on-resistance while enabling high-speed switching by shortening the depletion layer disappearance time and minimizing contact resistance, thus improving operational efficiency.
Implementation Method 1
an anode electrode that forms a Schottky junction with the semiconductor layer
Implementation Method 2
forms an ohmic junction with at least one of the first surface layer and the contact layer
Implementation Method 3
a semiconductor layer having a first conductive type, the semiconductor layer being epitaxially formed on a semiconductor substrate having the first conductive type
Data Source
AI summary
A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n−-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n−-type semiconductor layer. The anode electrode forms a Schottky junction with the n−-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.