Semiconductor Cell Array Subthreshold Neural Network Power
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Solution Overview
Problem
The miniaturization of transistors in product-sum operation circuits leads to increased shoot-through current, resulting in higher power consumption, which is a challenge for achieving high arithmetic processing performance per unit electric power, especially in applications like augmented reality devices where power efficiency is critical.
Innovation Solution
A semiconductor device with a cell array performing product-sum operations in an artificial neural network, utilizing a dual-layer structure with transistors and capacitors, where the first region processes t-th data and outputs (t+1)-th data, and the second region processes (t+1)-th data and outputs t-th data, with nonlinear operations and analog current output in the subthreshold region, using metal oxide and silicon semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to increase integration density in product-sum operation circuits, then the number of neurons and synapses can be increased, but shoot-through current increases leading to higher power consumption
Solution Approach 1:
The patent changes the operating parameters of transistors by utilizing subthreshold operation, where transistors operate below their threshold voltage. This allows the circuit to function at extremely low power levels while maintaining the miniaturized transistor structure, thereby resolving the contradiction between high integration density and low power consumption
Solution Approach 2:
The patent implements periodic operation modes where the circuit alternates between active computation phases and low-power standby phases. During standby, capacitors retain computed values without requiring continuous power supply to transistors, reducing average power consumption while maintaining arithmetic processing capability
2Productivity
If the number of memory elements is increased to perform more complex product-sum operations, then arithmetic processing performance is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
The patent merges the functions of memory storage and arithmetic computation into a single integrated structure. Memory elements serve dual purposes: storing weight values and performing product-sum operations through their electrical characteristics. This eliminates the need for separate memory and computation blocks, reducing overall circuit complexity while maintaining high arithmetic processing performance
Solution Approach 2:
Each memory element is designed to perform multiple functions: data storage, weight retention, and active participation in product-sum operations. This multi-functionality allows a single cell array to handle complex neural network computations without requiring additional dedicated circuitry for each operation type, thereby managing complexity efficiently
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances arithmetic processing performance per unit electric power, reduces power consumption, and enables efficient operation in low-power devices like augmented reality systems by optimizing the product-sum operations across multiple layers in a neural network.
Implementation Method 1
Each memory element of the product-sum operation circuit outputs a current corresponding to a product of data corresponding to a multiplier retained in each memory element and input data corresponding to a multiplicand by using operation in a subthreshold region of a transistor
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.