Semiconductor Cell Boundary Routing Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for designing semiconductor device layouts often result in inefficient use of space at cell boundaries, leading to routing issues and decreased integration density, which affects manufacturing costs and competitiveness.
Innovation Solution
A method involving the strategic placement and rearrangement of conductive lines across adjacent tracks at cell boundaries, using pre-conductive and post-conductive lines formed by different photomasks, to optimize routing and prevent routing problems while maintaining separation distances, allowing for efficient use of space and improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the layout is redesigned or area is increased to make better use of cell boundary area, then the routing efficiency at cell boundary is improved, but the manufacturing cost increases and competitiveness deteriorates
Solution Approach 1:
The patent divides the cell boundary routing problem into two separate photomask processes: pre-conductive lines formed by a first photomask and post-conductive lines formed by a second photomask. This segmentation allows independent optimization of each routing layer, improving routing efficiency at cell boundaries without requiring overall layout redesign that would increase manufacturing complexity and cost
Solution Approach 2:
The patent performs preliminary routing actions by forming pre-conductive lines adjacent to the cell boundary before forming the post-conductive lines. This preliminary placement of conductive lines enables subsequent routing operations to be more efficient without requiring additional area or complex redesign, thereby improving routing efficiency while maintaining cost-effectiveness
2Ease of manufacture
If the integration density is increased to reduce manufacturing costs, then the cost decreases, but the routing complexity at cell boundaries increases
Solution Approach 1:
By segmenting the routing into pre-conductive and post-conductive lines formed by different photomasks, the patent simplifies the routing process at cell boundaries even as integration density increases. Each photomask handles specific routing tasks, preventing routing complexity from escalating despite higher integration density
Solution Approach 2:
The patent changes the parameter of conductive line placement by positioning pre-conductive lines and post-conductive lines on specific non-adjacent tracks relative to the cell boundary. This parameter optimization enables efficient routing at cell boundaries while maintaining high integration density, thereby reducing manufacturing costs without increasing routing complexity
3Area of stationary object
If pre-conductive lines and post-conductive lines are disposed on adjacent tracks, then the space utilization is maximized, but routing problems occur at cell boundaries
Solution Approach 1:
The patent extracts the problematic adjacent track configuration and replaces it with a non-adjacent track arrangement. By taking out the pre-conductive and post-conductive lines from adjacent tracks and placing them on non-adjacent tracks, the patent eliminates routing problems at cell boundaries while maintaining efficient space utilization through optimized track selection
Solution Approach 2:
The patent introduces an intermediary spacing between pre-conductive and post-conductive lines by placing them on non-adjacent tracks. This intermediary arrangement acts as a mediator that prevents direct interference between the two conductive line types, thereby eliminating routing problems while still achieving efficient space utilization through careful track positioning
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.