Semiconductor Cell Structure With Deep Groove Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving low on-resistance while maintaining high breakdown voltage, particularly in high-voltage silicon power devices, due to difficulties in controlling charge balance and process implementation complexities, such as charge mismatch and instability in super junction structures.
Innovation Solution
A semiconductor cell structure comprising a highly-doped semiconductor material region, an epitaxial layer with a deep groove, a dielectric insulating layer, and semi-insulating material, where the semi-insulating material is in contact with the highly-doped region, optimizing electric field distribution and reducing on-resistance through improved charge balance and process simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional parallel-plane junction structures are used, then breakdown voltage is maintained, but on-resistance increases significantly (proportional to 2.5th power of breakdown voltage)
Solution Approach 1:
The patent transitions from conventional one-dimensional vertical junctions to two-dimensional junctions by forming PN junctions on the side surfaces of deep grooves. This dimensional change allows the current to flow through a larger effective area, reducing the on-resistance while maintaining the breakdown voltage through the vertical drift region.
Solution Approach 2:
The drift region is segmented into multiple regions by forming deep grooves that extend through it. These grooves create multiple parallel current paths and allow for the formation of multiple PN junctions, effectively dividing the current flow into several channels that reduce the overall on-resistance.
2Reliability
If super junction structures with deep grooves are implemented, then on-resistance is reduced, but process complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent introduces a dielectric insulating layer as an intermediary substance filling the deep grooves. This dielectric layer simplifies the manufacturing process by eliminating the need for complex oblique ion implantation and epitaxial filling required by conventional super junction structures, while still achieving the desired charge balance and electric field distribution.
Solution Approach 2:
The patent changes the material parameter from semiconductor (in conventional super junctions) to dielectric insulator for the groove filling material. This parameter change simplifies the manufacturing process since dielectric materials can be deposited using standard semiconductor fabrication techniques without requiring complex ion implantation angle control.
3Stress or pressure
If charge balance is strictly enforced in super junction structures, then breakdown voltage is optimized, but manufacturing precision requirements become extremely stringent
Solution Approach 1:
The patent uses a dielectric insulating layer with fixed charges that can be deposited in a single step using standard semiconductor processes. This approach replaces the complex multi-step process of forming precisely balanced semiconductor junctions, using a simpler, more robust material that achieves the same electric field modulation effect without stringent precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces on-resistance, enhances process implementation ease, and improves stability by inhibiting electric charge mismatch, achieving a 10 to 1000 times lower on-resistance compared to ideal parallel-plane junctions while maintaining high breakdown voltage, with reduced implementation costs and increased yield.
Implementation Method 1
a dielectric insulating layer is formed on a side wall inside the deep groove
Implementation Method 2
optimizing electric field distribution and reducing on-resistance through improved charge balance
Data Source
AI summary
A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.