Semiconductor Cell Layout Gap Filling Without Fillers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of filler cells to fill gaps between semiconductor die cells can alter the electrical characteristics of adjacent cells, leading to timing issues, necessitating a more effective approach to maintain circuit continuity without introducing non-functional cells.
Innovation Solution
Replacing one of the cells with a larger version of itself, functionally equivalent and extending its active regions by one gate pitch, to fill in the gap, thereby maintaining circuit functionality without the need for a filler cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If filler cells are used to fill gaps between cells, then the gap is filled and layout continuity is maintained, but the electrical characteristics of adjacent cells are altered and timing issues arise
Solution Approach 1:
The harmful filler cell is extracted and removed from the layout. Instead of using a non-functional filler cell that alters electrical characteristics, the patent extends an adjacent functional cell into the gap area, eliminating the need for a separate filler cell while maintaining layout continuity and preserving electrical characteristics.
Solution Approach 2:
The patent merges the gap-filling function with an adjacent functional cell by extending its active regions. This combines the original cell's functionality with the gap-filling role, eliminating the need for a separate filler cell and avoiding the electrical characteristic alterations that would result from introducing a non-functional filler cell.
2Ease of manufacture
If filler cells are used to fill gaps, then layout completeness is achieved, but timing performance deteriorates due to altered electrical characteristics
Solution Approach 1:
The harmful filler cell that causes timing issues is extracted and removed. The patent replaces it with an extension of an adjacent functional cell, maintaining layout completeness while preserving timing performance by avoiding the electrical characteristic alterations introduced by filler cells.
Solution Approach 2:
The patent changes the parameter of cell size by extending the active regions of an adjacent cell into the gap area. This parameter change allows the cell to serve dual purposes: maintaining its original functionality and filling the layout gap, thereby achieving layout completeness without the timing performance degradation caused by filler cells.
3Reliability
If cells are extended to fill gaps, then filler cells are eliminated and electrical characteristics are preserved, but the cell size increases
Solution Approach 1:
The patent merges the gap-filling function with an adjacent functional cell by extending its active regions. This combination allows the cell to maintain its original functionality while simultaneously filling the layout gap, preserving electrical characteristics without requiring a separate filler cell.
Solution Approach 2:
The extended cell serves multiple functions: it maintains its original circuit functionality and simultaneously acts as a gap-filler to maintain layout continuity. This multi-functionality eliminates the need for a separate filler cell and preserves electrical characteristics while achieving layout completeness.
Data Source
AI summary
In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.