Semiconductor Cell Gate Loop Design for Narrow Open Prevention
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Solution Overview
Problem
The miniaturization of semiconductors faces challenges in forming precise line and space patterns, particularly in forming cell gates, where the pattern ends can become narrow or break, leading to issues like narrow opens and short circuits, making it difficult to achieve the required pitch and size using existing lithographic and sidewall mask transfer technologies.
Innovation Solution
A semiconductor device design featuring cell gates formed with roughly rectangular closed loops or U-shaped open loops, connected between adjacent memory cell blocks, and a manufacturing method involving multiple hard masks and etching processes to create a line and space pattern with a sufficient pitch, allowing for wider cell gate gaps to accommodate contact adjustments and prevent narrowing or breaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sidewall mask transfer technology is used to form cell gates, then the pitch can be reduced to half of the dummy pattern pitch, but the pattern ends become narrow or break, causing narrow opens and short circuits
Solution Approach 1:
The cell gate pattern is segmented into multiple sections with varying widths. The pattern includes wider sections at the ends and narrower sections in the middle, allowing the ends to maintain sufficient width for reliability while the middle sections achieve the required pitch reduction. This segmentation resolves the contradiction by distributing different width requirements to different parts of the same pattern.
Solution Approach 2:
Different sections of the cell gate pattern are assigned different local qualities (widths). The end sections have larger width for reliability, while the middle sections have smaller width for pitch reduction. This local differentiation allows each part of the pattern to optimize for its specific functional requirement, resolving the contradiction between overall pitch reduction and local end integrity.
2Length of moving object
If lithographic technology is used for miniaturization, then the resolution limit is reached, but forming line and space patterns narrower than the resolution limit becomes difficult
Solution Approach 1:
Dummy patterns are formed first with a larger pitch that is within the lithographic resolution capability. Then, sidewall masks are formed on these dummy patterns, and the actual cell gate patterns are created by etching between the sidewalls. This preliminary formation of robust dummy patterns enables subsequent creation of narrower features that would be directly unformable by lithography alone.
Solution Approach 2:
The dummy patterns serve as an intermediary structure that mediates between the lithographic resolution limit and the desired final pattern dimensions. The sidewall masks formed on the dummy patterns act as intermediate masking elements that enable transfer of the pattern at half the original pitch, allowing indirect formation of features narrower than the direct lithographic limit.
3Length of moving object
If contact is arranged on narrow lines formed by sidewall mask transfer technology, then the adjustment margin becomes insufficient, making contact arrangement difficult
Solution Approach 1:
The cell gate pattern is segmented to include dedicated wider sections at the ends that are specifically suitable for contact arrangement. These segmented wider regions provide sufficient adjustment margin for contact positioning, while other parts of the pattern maintain the required narrow dimensions for high-density integration. This segmentation enables simultaneous achievement of narrow overall pitch and adequate contact arrangement flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of accurate and effective line and space patterns, prevents narrowing or breaking of cell gate ends, and allows for easier contact arrangement with a sufficient adjustment margin, thereby addressing the challenges of miniaturization and reducing manufacturing losses.
Implementation Method 1
etching a material to be processed using this sidewall pattern as a mask is performed
Implementation Method 2
depositing a first hard mask on a material to be processed
Data Source
AI summary
A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block.