Semiconductor Cell Height Reduction via Non-Integer Wiring Pitch

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Solution Overview

Problem

The existing design of semiconductor integrated circuit devices restricts the minimum size of standard cells due to the requirement that cell height must be an integer multiple of the wiring pitch, limiting further microfabrication and integration density.

Innovation Solution

The cell height is set to (an integer+0.5) or (an integer+0.25) times the second-layer wiring pitch, allowing for a non-integer multiple configuration that reduces the size of standard cells while maintaining wiring consistency, thereby increasing integration density and reducing the cell array area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the cell height is set to an integer multiple of the wiring pitch, then wiring consistency is improved, but the cell size cannot be reduced further

Engineering Contradiction:

Improvewiring consistencyVSAvoidcell size

Core Design Contradiction:

Manufacturing precisionVSArea of moving object

Solution Approach 1:

The patent changes the cell height parameter from an integer multiple of wiring pitch to a non-integer multiple (specifically 6.5 times the wiring pitch), enabling further cell size reduction while maintaining wiring consistency through adjusted tap positioning and wiring routing

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the cell height is reduced below integer multiple of wiring pitch, then integration density is improved, but wiring consistency deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoidwiring consistency

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent adopts a cell height of 6.5 times the wiring pitch (non-integer multiple), which increases integration density while maintaining wiring consistency through compensated tap positioning and adjusted wiring routing strategies

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent adjusts the vertical positioning of taps relative to the reduced cell height, using the second direction (vertical) to compensate for the non-integer cell height, thereby maintaining wiring consistency across cell boundaries

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8410526B2Semiconductor integrated circuit device with reduced cell size

Publication Date: 2013.04.02 RENESAS ELECTRONICS CORP

AI summary

A semiconductor integrated circuit device with reduced cell size including a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or (an integer+0.25×a wiring pitch of the second-layer wiring lines.