3D Semiconductor Cell Interconnect Layout for Higher Integration
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Solution Overview
Problem
The increasing demand for smaller, low-power, and high-performance semiconductor devices with enhanced data storage capacity poses challenges in manufacturing due to exponential increases in equipment costs and development time as metal line widths are reduced in two-dimensional planes, necessitating a transition to three-dimensional structures.
Innovation Solution
A semiconductor device manufacturing method involving the formation of adjacent cell areas with a support structure, where gate lines and pads are stacked and patterned to protrude along the support's sidewalls, allowing for electrical connections through connection pads, thereby reducing the number of process steps and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal line width is reduced in two-dimensional plane to increase data storage capacity, then integration density is improved, but manufacturing equipment costs and development period are exponentially increased
Solution Approach 1:
The patent transitions from two-dimensional metal line reduction to three-dimensional vertical stacking structure. Gate lines are stacked vertically with pads extending along sidewalls of support structures, enabling increased storage capacity through vertical integration rather than horizontal scaling, thereby avoiding exponential cost increases associated with further 2D miniaturization
2Quantity of substance
If metal line width is reduced in two-dimensional plane to increase data storage capacity, then integration density is improved, but development period is exponentially increased
Solution Approach 1:
By adopting vertical stacking architecture where gate lines and pads are arranged in three dimensions along sidewalls, the patent achieves higher storage capacity without the prolonged development cycles required for further 2D scaling. The vertical configuration enables parallel processing and simplified interconnect routing, reducing development time
3Ease of manufacture
If three-dimensional structure is used to reduce manufacturing costs and development time, then ease of manufacture is improved, but device complexity increases
Solution Approach 1:
The vertical stack structure is divided into distinct functional segments: gate lines stacked vertically, pads extending along sidewalls, and connection structures positioned at specific heights. This segmentation allows each component to be formed and processed independently using standard semiconductor manufacturing techniques, managing complexity while achieving cost reduction
Solution Approach 2:
The support structure with sidewalls serves multiple functions simultaneously: providing mechanical support, defining pad regions, enabling vertical stacking of gate lines, and facilitating electrical connections. This multi-functionality reduces the need for separate structural elements, simplifying manufacturing despite the 3D configuration
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes a first cell area and a second cell area adjacent to each other in a first direction, a support disposed between the first cell area and the second cell area, first gate lines stacked in the first cell area, first pads configured to extend from the first gate lines and configured to protrude upward along a first sidewall of the support, second gate lines stacked in the second cell area, second pads configured to extend from the second gate lines and configured to protrude upward along a second sidewall of the support, and first connection pads configured to extend in the first direction along a third sidewall of the support and configured to electrically connect the first pads with the second pads.