Semiconductor Cell Layout Clock Signal Routing via Widened Interconnects
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Solution Overview
Problem
Current Electronic Design Automation (EDA) tools have poor control over routing patterns on lower metal layers in semiconductor circuits, leading to Signal Electromagnetic (SEM) issues and design rule check (DRC) failures during clock signal routing, as they often occupy unnecessary resources and are affected by other signal wirings.
Innovation Solution
The implementation of tapping connectors with widened metal interconnects or interconnect-meshes on higher metal layers to create equivalent tapping points for clock signals, reducing current density and mitigating SEM noise, and allowing for easier clock tree routing while avoiding narrow path congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If EDA tools automatically route clock signals on lower metal layers, then routing is generated quickly, but SEM noise and DRC failures occur due to narrow path congestion and interference from surrounding wirings
Solution Approach 1:
The patent transitions clock signal routing from lower metal layers to higher metal layers, utilizing the vertical dimension of multi-layer interconnect structures. This dimensional shift allows clock signals to be routed on cleaner, less congested layers with fewer surrounding wirings, thereby reducing SEM noise while maintaining routing automation capabilities.
Solution Approach 2:
The patent applies different routing strategies to different metal layers: lower metal layers maintain traditional automatic routing for general signals, while higher metal layers are designated for clock signals with specialized widened paths. This local differentiation optimizes both routing speed and SEM performance in their respective layers.
2Device complexity
If clock signals are routed through narrow paths on lower metal layers, then routing resources are saved, but current density increases and SEM noise worsens
Solution Approach 1:
The patent changes the physical parameters of clock signal paths by widening them on higher metal layers. This parameter modification (increased path width) reduces current density and SEM noise while the automated routing tools manage the overall resource allocation to maintain efficiency.
3Ease of manufacture
If traditional automatic routing is used without intervention, then design process is simple, but routing patterns lack control and cause congestion
Solution Approach 1:
The patent segments the routing process into two distinct phases: automatic routing generation for overall path selection (maintaining simplicity), and manual/automated adjustment of clock signal paths on higher metal layers (enhancing control). This segmentation allows each phase to optimize for its specific requirements.
Data Source
AI summary
A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.