Semiconductor Cell Layout Orientation for Leakage Reduction
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Solution Overview
Problem
Current design rules for semiconductor devices fail to effectively reduce inter-cell-region current leakages in integrated circuits, leading to inefficiencies in semiconductor device performance.
Innovation Solution
A method of generating layout diagrams that involves populating rows with cells, arranging them to be substantially abutting, and reducing aggregate leakage by changing the orientation or location of cells, including replacing cells with mirror-symmetric versions, to minimize inter-cell leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cells are arranged to be substantially abutting in rows, then device integration density is improved, but inter-cell leakage current increases
Solution Approach 1:
The patent applies local quality by making the abutting interface between adjacent cells asymmetric. Specifically, the first cell has a first abutting interface and the second cell has a second abutting interface that is offset relative to the first interface in the second direction. This local asymmetry at the cell boundary prevents direct alignment of conductive paths while maintaining overall high integration density through compact cell arrangement.
Solution Approach 2:
The patent directly applies asymmetry by designing the abutting interfaces of adjacent cells to be non-aligned. The first abutting interface of a first cell and the second abutting interface of an adjacent second cell are positioned at different locations in the second direction, creating an asymmetric configuration that disrupts leakage current paths while preserving the abutting arrangement for high density.
2Manufacturing precision
If design rules are made specific to process technology node, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by introducing specific geometric parameters for cell interface arrangement. The design rules specify that adjacent cells should have offset abutting interfaces with defined offset distances in the second direction. These parameterized rules provide process variability compensation through controlled geometric relationships rather than through complex material or process specifications.
Data Source
AI summary
A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.