Semiconductor Cell Layout for Lower On-Resistance Sensing

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Solution Overview

Problem

The existing semiconductor device structure reduces the area of the principal current cell due to the area required for the bonding pad wiring layer of the sub-cell, leading to increased on-resistance and chip cost.

Innovation Solution

A semiconductor device design where the bonding pad wiring layer covers part of the principal current cell's electrode via an interlayer insulating film, allowing the sub-cell to be positioned at the same height, thereby increasing the principal current cell area without expanding the bonding pad wiring layer's area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bonding pad wiring layer is formed above the current detection cell as disclosed in PTL 1, then the sub-cell can be connected properly, but the area of the principal current cell is reduced

Engineering Contradiction:

Improveconnection reliabilityVSAvoidprincipal current cell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar arrangement where the bonding pad wiring layer is formed above the current detection cell to a three-dimensional arrangement where the sub-cell is positioned at the same height as the principal current cell. This vertical repositioning allows the bonding pad wiring layer to be formed without overlapping the principal current cell area, thereby resolving the area reduction problem while maintaining connection reliability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the sub-cell within the principal current cell structure by positioning it at the same height and using the interlayer insulating film to separate them. This nested arrangement allows both cells to coexist in the same vertical space without interfering with each other's area requirements, effectively resolving the area contradiction

Inventive Principle:

Principle #7Nested doll (Nesting)

2Ease of manufacture

If the area of the principal current cell is reduced, then the bonding pad wiring layer can be formed for the sub-cell, but the on-resistance increases

Engineering Contradiction:

Improvebonding pad wiring formationVSAvoidon-resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

By repositioning the sub-cell to the same height as the principal current cell rather than above it, the patent eliminates the need to reduce the principal current cell area to accommodate the bonding pad wiring layer. This maintains the full area of the principal current cell, thereby keeping on-resistance low while still enabling proper wiring formation for the sub-cell

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If the chip size is increased to accommodate both cells separately, then each cell can have sufficient area, but the manufacturing cost increases

Engineering Contradiction:

Improvecell areaVSAvoidmanufacturing cost

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent nests the sub-cell within the principal current cell structure by positioning it at the same height and using the interlayer insulating film to separate them. This allows both cells to share the same chip area without requiring additional chip size, thereby maintaining sufficient area for each cell while avoiding increased manufacturing costs

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent merges the spatial occupation of both cells by positioning them at the same height within the same chip area. This combined arrangement allows both cells to coexist efficiently without requiring separate dedicated areas, thereby reducing overall chip size and manufacturing cost while maintaining individual cell performance

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11855166B2Semiconductor device including sub-cell disposed at chip center

Publication Date: 2023.12.26 ASTEMO LTD

AI summary

There is a problem that an area of a principal current cell is reduced by an area of a bonding pad wiring layer for a sub-cell. A source electrode 9b of a current detection cell 22 is electrically connected to a bonding pad wiring layer 12 formed on an interlayer insulating film 10 via a wiring layer contact 11. The bonding pad wiring layer 12 is formed with respect to a source electrode 9a of a principal current cell 21 so as to cover a part of the source electrode 9a via the interlayer insulating film 10. As a result, the source electrode 9b is miniaturized, and a size of the source electrode 9b is made substantially equal to a size of the current detection cell 22. Therefore, the current detection cell 22 and the principal current cell 21 are disposed close to each other.