Semiconductor Cell Layout Using Subjacent Local Conductive Leads
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Solution Overview
Problem
Semiconductor device cells face limitations in accommodating additional metal tracks due to minimum spacing design rules, which restricts the integration level and complexity, requiring signal tracks to be added at the expense of power tracks, thereby limiting device performance.
Innovation Solution
The layout incorporates a void area in the polysilicon layer to form subjacent local conductive leads beneath the first metal interconnect level, allowing for additional signal lines without reducing power lines, thereby increasing the number of metal tracks that can be accommodated within a cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If minimum spacing design rules are followed for metal tracks, then spacing requirements are met, but the number of metal tracks that can extend through cells is limited
Solution Approach 1:
The patent introduces a second metal interconnect level (metal II) above the first metal interconnect level (metal I). This vertical stacking of metal tracks in multiple dimensions allows signal and power lines to be routed through different levels, effectively increasing the total number of tracks that can be accommodated within the same cell area while maintaining required spacing between tracks on each level.
2Area of stationary object
If cell size is reduced to increase integration levels, then chip area decreases, but metal track spacing becomes more constrained
Solution Approach 1:
The patent transitions from a two-dimensional planar routing approach to a three-dimensional stacked routing approach by introducing metal II above metal I. This vertical dimension allows the cell size to be reduced in the horizontal plane while maintaining adequate spacing between tracks by utilizing the vertical separation between metal levels, thus achieving higher integration without compromising spacing requirements.
Data Source
AI summary
Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.