Semiconductor Cell Layout With Matched Power Paths for Voltage Uniformity
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Solution Overview
Problem
The miniaturization of integrated circuits leads to increased design complexity and inconsistent voltage drops across semiconductor devices due to longer power travel distances, affecting the reliability and stability of circuit operations.
Innovation Solution
The implementation of a semiconductor cell structure with matched conductive paths on both sides of a substrate, ensuring that PMOS and NMOS transistors receive equal source voltages through conductive paths, which are designed to have equivalent impedances, thereby maintaining consistent voltage drops and current mirroring across the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power is provided from the backside of the substrate to reduce area requirements, then area efficiency is improved, but voltage drop consistency deteriorates due to increased travel distance
Solution Approach 1:
The power delivery path is segmented into two separate conductive paths: one for PMOS transistors and one for NMOS transistors. Each path is independently routed to ensure equal length and equivalent impedance, thereby maintaining consistent voltage drops despite power being delivered from the backside of the substrate.
Solution Approach 2:
The conductive paths are designed with locally optimized characteristics to match the specific requirements of PMOS and NMOS transistors. Each path has equivalent impedance tailored to its destination, ensuring that voltage drops remain consistent across different transistor types while still benefiting from backside power delivery.
2Ease of operation
If conductive paths are extended to reach devices on the substrate, then device connectivity is improved, but voltage drop consistency deteriorates
Solution Approach 1:
While the overall path lengths are made equal, the conductive paths exhibit asymmetric routing patterns to accommodate the different locations of PMOS and NMOS transistors on the substrate. This asymmetric design allows each path to be optimized for its specific route while maintaining equal total length and equivalent impedance.
Solution Approach 2:
The conductive paths are designed to maintain equipotential conditions at their endpoints by ensuring equal path lengths and equivalent impedances. This approach ensures that both PMOS and NMOS transistors receive the same source voltage despite the extended travel distance required to reach devices on the substrate.
3Quantity of substance
If path length is increased to connect more devices, then device coverage is improved, but voltage drop variation worsens
Solution Approach 1:
The conductive paths are designed to maintain equipotential conditions at their endpoints by ensuring equal path lengths and equivalent impedances. This approach ensures that both PMOS and NMOS transistors receive the same source voltage despite the extended travel distance required to reach devices on the substrate.
Solution Approach 2:
The impedance parameters of the conductive paths are carefully adjusted and matched to ensure equivalent impedance values. By changing and optimizing the impedance parameters rather than simply minimizing path length, the design achieves both extended device coverage and uniform voltage drops across all connected devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the output signal by ensuring that currents and voltages are consistent across the semiconductor devices, reducing the impact of temperature changes and improving the overall performance and reliability of the integrated circuits.
Implementation Method 1
The first conductive path comprises a first conductive via and a first conducting element. The first conductive via extends from a second region on the first surface to the second surface of the substrate. The first conductive via is coupled to receive a reference voltage from a conductive layer below the second surface
Implementation Method 2
designed to have equivalent impedances, thereby maintaining consistent voltage drops and current mirroring across the devices
Data Source
AI summary
A semiconductor cell structure includes a first complementary metal oxide silicon (CMOS) a second CMOS, a first conducting element, and a second conducting element. The first and second CMOSs are disposed on the substrate and a reference voltage is provided to the first CMOS and the second CMOS respectively through the first conducting element and the second conducting element. A product of a width of the first conducting element multiplied by a channel length of the first CMOS is positively related to a product of a width of the second conducting element multiplied by a channel length of the second CMOS.