Semiconductor Cell Layout for Metal ECO Without Mask Rework
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device design and manufacturing processes lead to increased development costs and extended development periods due to changes in circuit design after mask creation, necessitating rework on device masks and interconnect masks.
Innovation Solution
The implementation of ECO base cells and through cells in the layout design, allowing for changes in circuit function without altering transistor placement by modifying interconnect layouts, and using through cells to alleviate interconnect congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If circuit design changes are made after mask creation, then design adaptability is improved, but manufacturing cost increases and development time extends due to rework on device masks and interconnect masks
Solution Approach 1:
The patent segments the cell structure into fixed transistor components and flexible interconnect components. The transistor layout remains fixed on the device mask, while the interconnect layout can be independently modified on the interconnect mask to implement circuit design changes, thereby avoiding costly rework of device masks.
Solution Approach 2:
The interconnect layout is made dynamic and adjustable after mask creation. Through ECO base cells and through cells, the interconnect routing can be reconfigured to implement circuit design changes without altering the fixed transistor layout, enabling adaptability while maintaining manufacturing efficiency.
2Adaptability or versatility
If circuit design changes are made after mask creation, then design adaptability is improved, but development time extends due to rework requirements
Solution Approach 1:
By separating device mask and interconnect mask functionalities, the patent enables independent modification of interconnect routing without affecting device mask production timing. This segmentation allows parallel processing and reduces sequential rework time.
Solution Approach 2:
The fixed transistor layout is established in advance on the device mask before interconnect routing is finalized. This preliminary action allows interconnect changes to be made later through ECO base cells and through cells without requiring device mask rework, significantly reducing development time.
3Ease of manufacture
If traditional cell structures are used, then manufacturing simplicity is maintained, but interconnect congestion occurs and coupling efficiency decreases
Solution Approach 1:
The patent introduces universal ECO base cells and through cells that can be integrated into traditional cell structures. These multi-functional elements provide additional interconnect routing paths and coupling options without complicating the basic cell structure, thereby improving interconnect coupling efficiency while maintaining manufacturing simplicity.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
According to an embodiment, a semiconductor device includes a first cell. The first cell includes, a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side by side with the first NMOS transistor, and a seventh interconnect not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.