Semiconductor Cell Block Layout With Non-Integer Cell Heights
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Solution Overview
Problem
Existing semiconductor cell blocks typically have uniform or integer multiple heights, limiting their ability to support diverse device architectures and drive cells, and do not efficiently utilize layer stacking patterns to optimize cell heights and widths.
Innovation Solution
A semiconductor cell block design featuring layers of varying heights, where the second height is a non-integer multiple of the first height, allowing for both lower and taller logic cells with different device architectures, and including a method for generating layouts using placement and routing tools to optimize layer arrangements and power rail placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform or integer multiple heights are used for semiconductor logic cells, then manufacturing simplicity and layout regularity are improved, but adaptability to diverse device architectures and optimization of cell heights and widths deteriorate
Solution Approach 1:
The semiconductor cell block is segmented into multiple layers with different height characteristics. First layers have a first height suitable for low drive cells, while second layers have a second height (non-integer multiple of the first height) suitable for high drive cells. This segmentation allows each layer to be optimized for specific device architectures without compromising overall manufacturing regularity.
Solution Approach 2:
Different regions (layers) of the semiconductor cell block are assigned different height qualities. The first layers provide a baseline height for standard logic cells, while the second layers provide increased height for high drive cells requiring greater vertical space. This local differentiation enables diverse device architectures to coexist within the same cell block while maintaining systematic manufacturing approaches.
2Device complexity
If integer multiple heights are used for semiconductor logic cells, then layer stacking simplicity is improved, but optimization of cell heights and widths for performance deteriorates
Solution Approach 1:
The height parameter of the second layers is changed from integer multiples of the first height to non-integer multiples. Specifically, the second height is configured as a non-integer multiple (e.g., 1.5 times, 1.7 times) of the first height, enabling fine-tuned optimization of cell heights and widths for high drive cells while maintaining manageable layer stacking patterns through systematic arrangement.
Data Source
AI summary
A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.