Semiconductor Device Cell Pitch Reduction via Vertical Source Region
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Solution Overview
Problem
Existing semiconductor devices face limitations in reducing on-state resistance (RON) due to constraints in reducing cell pitch without rendering other components inoperable, as a sufficiently sized source region is required for normal MOSFET operations.
Innovation Solution
A semiconductor device structure is fabricated with a reduced cell pitch by forming trenches at a predetermined pitch, where a gate electrode partially fills each trench, and conductivity type regions are formed without a separate mask for the active region, allowing for an adequately sized N+ source region and minimal semiconductor resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If cell pitch is reduced to lower on-state resistance, then on-state resistance decreases, but source region size becomes insufficient for normal MOSFET operations
Solution Approach 1:
The source region is formed not only in the horizontal plane between trenches but also extends vertically into the substrate. This three-dimensional source region configuration allows sufficient source area for normal MOSFET operations even when the horizontal cell pitch is reduced to 0.4-0.6 μm, thereby lowering on-state resistance without sacrificing source region functionality
Solution Approach 2:
The source region is segmented into multiple portions: a first conductivity type region in the upper surface portion between trenches, and a second conductivity type region in the side surface of the substrate between trenches. This segmentation allows optimization of current flow paths and reduces on-state resistance while maintaining adequate total source area
2Manufacturing precision
If separate mask steps are used to form conductivity type regions, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The formation of the first conductivity type region and the second conductivity type region is merged into a single ion implantation process without requiring separate masks. The ion implantation conditions (energy, dose, angle) are optimized to automatically form both regions with correct doping profiles, eliminating multiple masking steps and reducing manufacturing complexity while maintaining precision
Solution Approach 2:
By changing ion implantation parameters (energy levels, doping doses, implantation angles), the process forms both the first conductivity type region in the upper surface and the second conductivity type region in the side surface simultaneously. This parameter optimization allows precise control of doping profiles without additional masking steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables a semiconductor device with minimal cell pitch and reduced on-state resistance, maintaining operational effectiveness and reducing manufacturing costs by eliminating the need for separate masking steps.
Implementation Method 1
At least one of the first conductivity type region and the second conductivity type region may be formed by ion implanting without using a mask for blocking the active region
Data Source
AI summary
A method for fabricating a semiconductor device is disclosed. A plurality of trenches is formed at a predetermined cell pitch in an upper surface portion of a substrate. A first insulation film is formed on the substrate. A gate electrode is formed and partially filled within each trench. A first conductivity type region is formed in the upper surface portion of the substrate between the trenches. A second conductivity type region is formed in a side surface of the substrate between the trenches and the first conductivity type region. A second insulation film is formed covering the gate electrode within each trench, wherein an upper surface of the second insulation film is positioned lower than an upper surface of the substrate. A source metal layer is formed on the second insulation film and electrically connected to the first conductivity type region and the second conductivity type region.